Capacitor, semiconductor memory device, and method for...

Details Capacitor, semiconductor memory device, and method for... Capacitor, semiconductor memory device, and method for...

2002-06-21

2004-05-04

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S297000, C257S306000, C257S311000

Reexamination Certificate

active

06730951

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a capacitor using a metal oxide in a capacitor insulating film, a semiconductor memory device using such a capacitor, and a method for manufacturing the same.
In recent years, along with developments in the digital technology for electronic equipment, the amount of data to be processed and stored has been increasing. Meanwhile, the level of functionality required for such electronic equipment has also been increasing, and the size of a semiconductor device used in electronic equipment and the size of a semiconductor element used in the semiconductor device have been rapidly reduced.
Along with this trend, techniques have been widely researched and developed in the art that allow the use of a high-permittivity dielectric material as a capacitor insulating film, instead of using silicon oxide or silicon nitride as in the prior art, in order to realize a higher degree of integration of a dynamic RAM device, for example.
Furthermore, ferroelectric films, which are spontaneously polarized, have been actively researched and developed in the art, aiming to realize a non-volatile RAM device that operates at a lower voltage than in the prior art and is capable of performing high-speed write and read operations. In a semiconductor memory device using such a high-permittivity dielectric material or a ferroelectric material in a capacitor insulating film, stacked memory cells have been used, instead of using planar memory cells as in the prior art, for highly-integrated memory devices whose storage capacity is on the order of megabits.
A conventional semiconductor memory device will now be described with reference to the drawings.
FIG. 15
is a cross-sectional view illustrating an important part of a conventional semiconductor memory device disclosed in Japanese Laid-Open Patent Publication No. 11-8355.
As illustrated in
FIG. 15
, the conventional semiconductor memory device includes a transistor
105
, which includes source/drain regions
102
formed in an upper portion of a semiconductor substrate
101
, and a gate electrode
104
formed over a channel region of the semiconductor substrate
101
via a gate insulating film
103
. An interlayer insulating film
106
is formed on the semiconductor substrate
101
so as to cover the entire surface thereof including the transistor
105
, and a contact plug
107
electrically connected to one of the source/drain regions
102
is formed in the interlayer insulating film
106
.
An insulating hydrogen barrier layer
108
made of silicon nitride (Si
3
N
4
) is formed on the interlayer insulating film
106
, and a conductive hydrogen barrier layer
109
made of titanium nitride (TiN) is formed on an upper end of the contact plug
107
.
A lower electrode
110
containing iridium dioxide (IrO
2
) or ruthenium dioxide (RuO
2
) is formed on the insulating hydrogen barrier layer
108
so as to be connected to the conductive hydrogen barrier layer
109
.
A buried insulating film
111
made of silicon oxide (SiO
2
), silicon nitride (Si
3
N
4
), silicon oxynitride (SiON), etc., is formed on the insulating hydrogen barrier layer
108
between the lower electrodes
110
.
A capacitor insulating film
112
made of a ferroelectric material such as lead zirconate titanate (Pb(Zr, Ti)O
3
) or strontium bismuth tantalate (SrBi
2
Ta
2
O
9
) is formed on the buried insulating film
111
including the lower electrode
110
, and an upper electrode
113
containing iridium dioxide or ruthenium dioxide is formed on the capacitor insulating film
112
. Moreover, an insulating hydrogen barrier layer
114
made of silicon nitride, etc., is formed on the upper electrode
113
.
However, the conventional semiconductor memory device as described above has two problems as follows.
First, the conductive oxide film of the lower electrode
110
, which is made of iridium dioxide or ruthenium dioxide and serves as a barrier against oxygen, is reduced by hydrogen that is generated during the manufacturing process, whereby the barrier property thereof against oxygen is deteriorated.
Second, the high-permittivity dielectric material or the ferroelectric material of the capacitor insulating film
112
is reduced by hydrogen that is generated during the manufacturing process, whereby the electrical characteristics thereof as a capacitor are deteriorated.
The first problem, i.e., the reduction of the lower electrode having an oxygen barrier property during the manufacturing process, will first be described with reference to FIG.
16
A and FIG.
16
B.
As illustrated in
FIG. 16A
, when a buried insulating film
111
A is deposited after patterning the lower electrode
110
containing iridium dioxide or ruthenium dioxide, hydrogen ions are generated from monosilane (SiH
4
) or ammonia (NH
3
), which is a material gas, and iridium dioxide or ruthenium dioxide is easily reduced by the hydrogen ions. The reduction reaction is particularly pronounced in a case where a plasma CVD method is used for depositing the buried insulating film
111
A.
As a result, the diffusion barrier property against oxygen atoms in the buried insulating film
111
is deteriorated. Therefore, during an oxygen annealing process performed at about 650° C. to 800° C., which is necessary for crystallization of the capacitor insulating film
112
, which is made of a high-permittivity dielectric material or a ferroelectric material and formed on the lower electrode
110
, oxygen ions diffused from the capacitor insulating film
112
are diffused through the lower electrode
110
to reach the interface between the lower electrode
110
and the contact plug
107
, as illustrated in FIG.
16
B. This causes a contact failure, e.g., an increase in the contact resistance.
Next, the second problem, i.e., the reduction of the capacitor insulating film made of a high-permittivity dielectric material or a ferroelectric material during the manufacturing process, will be described with reference to FIG.
17
.
In an actual semiconductor memory device, a plurality of capacitors and transistors are both arranged two-dimensionally in a so-called “array pattern”, as illustrated in
FIG. 15
or FIG.
17
. In a case where the capacitor insulating film
112
of the capacitors, which are arranged in an array pattern, is made of a high-permittivity dielectric material or a ferroelectric material, a metal oxide is used in many cases, as described above. Therefore, it is not possible to prevent some of the capacitors arranged in an array pattern that are located along a periphery
100
of the array pattern from being reduced by hydrogen ions, only with the insulating hydrogen barrier layer
108
provided under the capacitors and the insulating hydrogen barrier layer
114
provided over the capacitors, for the following reason. As illustrated in
FIG. 17
, although the diffusion of hydrogen ions into the capacitors in the upward direction and the downward direction of the semiconductor substrate
101
can be prevented, it is not possible to prevent the diffusion of hydrogen ions in a lateral direction, i.e., in a direction parallel to the substrate plane, into those capacitors that are located along the periphery
100
.
Japanese Laid-Open Patent Publication No. 2001-237393 discloses a semiconductor memory device in which a capacitor is covered completely with a hydrogen barrier layer. However, in a semiconductor memory device in which a plurality of capacitors are arranged in a two-dimensional array pattern, the deterioration of the characteristics of the capacitors cannot be prevented unless all of the plurality of capacitors are covered completely with the hydrogen barrier layer.
Moreover, Japanese Laid-Open Patent Publication No. 11-126881 discloses a semiconductor memory device in which a plurality of capacitors are covered completely with a hydrogen barrier layer. However, this publication does not disclose means for applying a voltage to an upper electrode
110
shown in
FIG. 1
of the publication. Assuming that a contact hole is provided for the application of a voltage to the

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