Capacitor-plate bias generator for CMOS DRAM memories

Details Capacitor-plate bias generator for CMOS DRAM memories Capacitor-plate bias generator for CMOS DRAM memories

1986-08-19

1988-09-06

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Capacitors

365189, 365226, 307297, G11C 1124

Patent

active

047697849

ABSTRACT:
A capacitor-plate bias generator produces a voltage on the capacitor plate node which consists of a constant voltage plus the sense-level voltage. Consequently, the capacitor-plate node tracks any variations in the sense-level voltage. The constant voltage is 3V.sub.BG, or 3 times the bandgap voltage of silicon. The circuit includes a reference-voltage source which produces the sum of the sense-level voltage and V.sub.BG, and a feedback control circuit for enabling either a charge pump or a charge bleeder to regulate the capacitor-plate voltage at a level above the circuit supply voltage.

REFERENCES:
patent: 3909631 (1975-09-01), Kitagawa
patent: 4259729 (1981-03-01), Tokushige
patent: 4375596 (1983-03-01), Hoshi
patent: 4581546 (1986-04-01), Allan
patent: 4593382 (1986-06-01), Fujishima et al.
patent: 4670861 (1987-06-01), Shu et al.

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