Capacitor over bitline DRAM cell

Details Capacitor over bitline DRAM cell Capacitor over bitline DRAM cell

1996-06-26

1997-09-23

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Capacitors

365 51, 257296, 257908, G11C 1124

Patent

active

056711751

ABSTRACT:
A DRAM array (100) having reduced bitline capacitance. The DRAM cell includes a pass transistor and a storage capacitor (150). An isolation structure (108) surrounds the DRAM cell. The bitline (140) is connected to a source/drain region (120b) of the pass transistor using a first polysilicon plug (112). A second polysilicon plug (110) connects the storage capacitor (150) to the other source/drain region (120a&c) of the pass transistor. Both polysilicon plugs (110, 112) extend through an interlevel dielectric layer (116) to one of the source/drain region (120a-c) of the pass transistor, but neither extends over the isolation structure (108). If desired, either the storage capacitor (150) or the bitline (140) may be offset from the source/drain regions (120a-c).

REFERENCES:
patent: 5291433 (1994-03-01), Itoh
patent: 5392232 (1995-02-01), Kim et al.

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