Capacitor over bit line memory cell and process

Details Capacitor over bit line memory cell and process Capacitor over bit line memory cell and process

2000-03-16

2001-12-11

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S906000

Reexamination Certificate

active

06329682

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to capacitor over bit line structures for memory cells, such as dynamic random access memory (DRAM) cells, and to methods for fabricating such structures and cells.
2. Description of the Related Art
As memory cell density increases, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. One way of increasing cell capacitance is through three-dimensional cell capacitor structures, such as trenched or stacked capacitors.
Stacked capacitor DRAMs utilize either a buried bit line or a non-buried bit line structure. With buried bit line structures, bit lines are provided in close vertical proximity to the bit line contacts of the memory cell field effect transistors (FETs), and the cell capacitors are formed horizontally over the top of the word lines and bit lines. Buried bit line structures, sometimes referred to as capacitor-over-bit-line (COB) structures, are the subject of this invention.
Sim et al., “A New Planar Stacked Technology (PST) for Scaled and Embedded DRAMs,” IEEE, IEDM 96-597-600 (1996), refers to a COB type DRAM structure made by a process of inserting a connecting layer between a storage node contact and a gate polysilicon layer. After formation of a tungsten damascene bit line, the storage node contact is opened and a polysilicon plug is formed by deposition and etch-back. Capacitors are formed by oxide etch selective to storage node hole formation, followed by polysilicon deposition and CMP for cylindrical capacitor definition. The cell plate is then patterned, followed by W-plug CMP and metalization.
M. Sakao et al., “A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs,” IEEE, IEDM 90-655-658 (1990), refers to a process for making a COB cell wherein, after opening a self-aligned contact to the active area, a polysilicon layer is formed as a local interconnect. After an insulating interlayer deposition, a bit line contact is opened and filled with a doped polysilicon plug. A polycide bit line is then formed, and an insulating interlayer is deposited on the bit line and planarized. After opening the capacitor contact, an HSG polysilicon storage node is formed and connected to the active area through the capacitor contact and local interconnect.
The goal of increasing or, at least, maintaining cell capacitance as cell size shrinks must be attained without resorting to processes that increase the number of masking, deposition, etch and other steps in the production process. This has a great impact on manufacturing costs, particularly the costs of photolithographic steps. High capital costs are associated with photolithographic equipment and more complex photo processing, in terms of more photo process steps per level, more equipment, and the use of expensive ultra clean room floor space. Defect density is inevitably increased with each additional photomasking layer and compromises yield and reliability. All photo layers also require a subsequent step, either implant or etch. These additional steps further add to manufacturing costs.
What is needed is a capacitor over bit line cell of reduced complexity that can be fabricated with a minimum of process steps.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a buried bit line stacked-capacitor memory cell by a process that reduces the number of photomasking and etching steps.
A further object of the present invention is to provide a method for fabricating a buried bit line memory cell having a bit line, plugs for the future capacitors, and plugs of slots in the periphery for shallower contacts, which can all be formed in a single processing step.
Yet a further object of the present invention is to provide a DRAM cell with a stacked capacitor over silicided bit line structure having reduced complexity and thus reduced defect density, increased ease of manufacture, and reduced manufacturing cost.
These and other objects of the present invention are achieved by providing a method of forming a capacitor over bit line memory cell by:
providing an array of substantially electrically isolated word lines atop a semiconductor wafer;
providing active areas about the word lines to define an array of memory cell field effect transistors (FETs), the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line;
providing a first layer of electrically insulating material over the word lines and active regions, the layer of insulating material having an uppermost surface which is above the word lines;
providing first and second respective contact openings through the first insulating material layer to the first and second active regions;
providing a first layer of electrically conductive material over the first insulating material and within the first and second contact openings;
removing a portion of the first conductive material to outwardly expose remaining first insulating material, and to outwardly expose remaining first electrically conductive material within the first contact opening at an uppermost surface of said remaining first conductive material which is elevationally below the surface of the remaining first insulating material;
providing a second conductive layer and a bit line insulating material outwardly of the first layer of electrically conductive material;
providing a third layer of electrically conductive material having an uppermost surface above the bit line; and
removing a portion of the third electrically conductive layer selective to the underlying bit line insulating material to form a capacitor storage node.
In another embodiment the present invention provides a method of forming a capacitor over bit line memory cell by:
providing a silicon semiconductor substrate having a word line and an active area;
providing a first insulating material layer over the word line and active area;
opening first and second contact holes through the first insulating layer to a first contact location and a second contact location of the active area;
providing a first conductive material layer over the first insulating material and within the first and second contact holes;
removing a portion of the first conductive material layer to expose an outward surface of the conductive material at an elevation below the elevation of the outward surface of the first insulating material to form a bit line contact above the first contact location and an isolated conductive material plug above the second contact location; and
providing a capacitor atop the bit line contact and in electrical contact with the second active area through the plug.
According to another embodiment, the present invention provides a semiconductor processing method of forming a capacitor over bit line by:
providing a first and second opening in an insulating layer on a substrate;
providing an electrically conductive overlying layer to fill said first and second openings and form first and second electrically conductive pillars;
removing a portion of said first electrically conductive pillar to outwardly expose a surface of the first electrically conductive pillar which is elevationally below said insulating layer and second pillar;
capping said second pillar to form a bit line;
providing a second electrically conductive material over said bit line and in contact with said first pillar to form a capacitor storage node;
providing a dielectric layer over said storage node; and
providing an electrically conductive outer capacitor plate atop said dielectric layer.
In yet another embodiment, the present invention provides a stacked capacitor memory cell comprising a semiconductor substrate having word lines with an insulating material overlaying the substrate and word lines except at bit line contact and storage node contact locations of the substrate;
a polysilicon bit line contact and polysilicon storage node contact in el

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