Capacitor mismatch independent gain stage for differential...

Details Capacitor mismatch independent gain stage for differential... Capacitor mismatch independent gain stage for differential...

2002-12-09

2003-09-09

Young, Brain (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S172000

Reexamination Certificate

active

06617992

ABSTRACT:

FIELD OF THE INVENTION
The present invention related to the field of analog to digital converters, and in particular, to a method and apparatus directed to multistage pipelined analog to digital converters with improved performance when subject to capacitor mismatches.
BACKGROUND OF THE INVENTION
An analog-to-digital converter (ADC) is a device that takes an analog data signal and converts it into a digital code, i.e. “digitizes” the analog signal. Since the mid-1970's analog-to-digital converters have employed a variety of architectures, such as the integrating, successive-approximation, flash, and the delta-sigma architectures. Recently, the pipelined analog-to-digital converter (ADC) has become a popular ADC architecture for use in high-speed applications such as CCD imaging, ultrasonic medical imaging, digital videos, cable modems, and fast Ethernets. Pipelined ADCs are typically chosen because of their high accuracy, high throughput rates, and low power consumption. Moreover, the pipeline architecture generally provides better performance for a given power and die area than other ADC architectures.
An example of a conventional k-stage pipelined ADC (
100
) is shown in FIG.
1
. As shown in the figure, the conventional k-stage pipelined ADC (
100
) includes an array of k gain stages (
102
) and a decoder logic circuit (
104
). Each of the gain stages (
102
) is connected in series to the previous gain stage (
102
). Each gain stage (
102
) is also connected to the decoder logic circuit (
104
).
In operation, an analog input voltage (V
in
) is provided to the first gain stage (
102
). The first gain stage (
102
) samples the analog input voltage (V
in
) and converts it to a first digital coefficient (n
1
). The first coefficient (n
1
) is processed by the decoder logic circuit (
104
) to provide the Most Significant Bit (MSB) of a digital data representation of the analog input voltage (V
in
). The first gain stage (
102
) also converts the first digital coefficient (n
1
) back to an analog representation. The analog representation is subtracted from the sampled analog input voltage (V
in
) and multiplied by a gain multiplier to provide a “residue” voltage. The residue voltage (V
res
(
1
)) from the first gain stage (
102
) becomes the analog input voltage to the next gain stage (
102
) of the pipeline. That is, V
in
(
2
)=V
res
(
1
). The residue voltage (V
res
(i)) continues through the pipeline of gain stages (
102
), providing another digital coefficient (n
i
) based on the digital representation of the input to that gain stage, as described above.
The overall digital representation of the analog voltage input (V
in
) is obtained by concatenating the k digital coefficients (n
l
through n
k
) from the array of k gain stages (
102
) through the decoder logic circuit (
104
).
Digital error correction logic is typically used to improve the accuracy of conversions by providing overlap between the quantization ranges of adjacent gain stages (
102
) in the pipeline. An architecture that makes use of this correction to a 1-bit per stage pipeline ADC is a 1.5-bit per stage pipeline topology.
FIG. 2
is a graph illustrating ideal transfer characteristics of a 1.5-bit per stage conventional pipeline ADC such as illustrated in FIG.
1
. In the 1.5-bit architecture, there are two thresholds or transition points in the transfer curve, resulting in three operating regions. Each stage of the 1.5-bit architecture effectively converts only one bit of information. The extra region (as compared to a 1-bit per stage topology) is used for redundancy. That is, the extra bit of information is combined with the digital outputs from subsequent gain stages (
102
) in the pipeline to generate another bit.
As shown in
FIG. 2
, the input voltage (V
in
) appears along the x-axis and illustrates that the resolvable input range of the ADC is given by: −V
ref
<V
in
<+V
ref
.
Two transition points appear along the x-axis. The first transition point occurs at V
in
equal to −V
ref
/4 and the second transition point occurs at V
in
equal to V
ref
/4. The two transition points divide the operating range for the input voltage (V
in
) into three operating regions, where two bits (00, 01, and 10) of the digital output of each stage characterize the entire range. Further, the slope of each curve reflects the gain multiplier employed in the gain stage (
102
) of FIG.
1
.
Operationally, the gain stage (
102
) examines the input (V
in
(i)) and determines whether the input is less than the first transition point, −V
ref
/4. If V
in
(i) is less than the first transition point (−V
ref
/4) then the digital code output for the gain stage (
102
) is 00. Similarly, a digital output code of 01 is generated for V
in
(i) between the first transition point, −V
ref
/4, and the second transition point (V
ref
/4). If V
in
(i) is greater than the second transition point, V
ref
/4, the ideal transfer characteristics generates a digital output code of 10.
Moreover, the output residue voltage (V
res
(i)) is generated by the following transfer function:
V
res
(
i
)=2
M
·V
in
(
i
)−
D
i
·V
ref
  (EQ 1)
where M is the number of effective bits that are being generated by stage i, 2
M
represents the gain multiplier for the gain stage (
102
), and D
i
is a constant determined by the digital representation of the analog input voltage (V
in
), having possible values of −1, 0, and 1. For the 1.5-bit per stage ADC, the number of effective bits (M) is one. The output residue voltage (V
res
(i)) generated at the i
th
gain stage (
102
) becomes the analog input voltage (V
in
(i+1)) to the next gain stage (
102
).
SUMMARY OF THE INVENTION
The present invention is directed to a method and apparatus that produces a pipelined analog-to-digital converter (ADC) with improved linearity for a given capacitor mismatch, while retaining comparator offset margins. A capacitor circuit is selectively switched into the feedback position of a switched capacitor amplifier circuit depending on the region of operation of an input signal in a pipeline stage. There is a one-to-one correspondence between the number of capacitor circuit to be employed in the feedback and a given number of operating regions. An appropriate selection of comparator circuits' reference signals is employed to retain comparator-offset margin, while reducing the linearity errors resulting from capacitor mismatch.
In accordance with one embodiment of the present invention, an apparatus is directed to producing digital output signals from an analog input signal in a pipelined stage that includes a sample mode and a hold mode. The apparatus includes a first capacitor circuit, a second capacitor circuit, a third capacitor circuit, a comparator circuit, an amplifier circuit, and first and second selection circuits. The first capacitor circuit is coupled to the analog input signal during the sample mode such that the first capacitor circuit is charged by the analog input signal. The second capacitor circuit is coupled to the analog input signal during the sample mode such that the second capacitor circuit is charged by the analog input signal. The third capacitor circuit is coupled to a circuit ground potential during the sample mode such that the third capacitor is discharged. The comparator circuit is coupled to the analog input signal, and first and second sampling reference signals that are pre-selected to minimize transition height errors, the comparator circuit providing an output code in response to the analog input signal and the first and second sampling reference signals, wherein the output code correspond to one of at least three operating regions for the analog input signal during the sample mode. The amplifier circuit is coupled to the first, second, and third capacitance circuits during the hold mode. The first selection circuit is arranged to couple a selected one of the first, second, and third capacitance circuits between an input and an output of the amplifier circuit in response

Affiliated with

Also associated with

Rating

Capacitor mismatch independent gain stage for differential... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Capacitor mismatch independent gain stage for differential..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Capacitor mismatch independent gain stage for differential... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3026689