Capacitor loaded memory cell

Details Capacitor loaded memory cell Capacitor loaded memory cell

1998-11-09

2000-03-14

Nelms, David

Static information storage and retrieval

Systems using particular element

Flip-flop

365218, 365149, 365188, G11C 1100

Patent

active

060381639

ABSTRACT:
An apparatus and method for constructing a capacitor loaded memory cell. This capacitor loaded memory cell operates as a static random access memory (SRAM) cell if a particular capacitor and transistor configuration is used. Normally, capacitors are not an obvious choice as a load device for a memory cell because the intrinsic nature of capacitors is one that blocks the flow of direct current, the invention takes into account the secondary effects such as leakage of a particular dielectric used in the construction of the capacitor to modify the current blocking nature of the capacitor.

REFERENCES:
patent: 5283500 (1994-02-01), Kochanski
patent: 5485420 (1996-01-01), Lage et al.
patent: 5576240 (1996-11-01), Radosevich et al.
patent: 5696394 (1997-12-01), Jones, Jr. et al.
patent: 5739564 (1998-04-01), Kasa et al.
patent: 5825684 (1998-10-01), Lee
"A 2.9 .mu.m.sup.2 Embedded SRAM Cell with Co-Salicide Direct Strap Technology for 0.18 .mu.m mHigh Performance CMOS Logic," by K. Noda, K. Matsui, K. Inoue, T. Itani, H. Iwasaki, K. Urabe, H. Miyamoto, K. Tokashiki, H. Kawamoto, M. Satoh, K. yoshida, K. Kishimoto, K. Koyanagi, T. Tanigawa, ICDM Digest of Tech papers, Dec. 1987.
Article Untitled, by P. W. Diodato, J. T. Clemens, W. W. Troutman, W. S. Lindenberger, CICC Digest of Tech Papers, May 1997.

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