Capacitor-less memory cells and cell arrays

Details Capacitor-less memory cells and cell arrays Capacitor-less memory cells and cell arrays

2011-04-05

2011-04-05

Phung, Anh (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S401000, C257SE27084

Reexamination Certificate

active

07919800

ABSTRACT:
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

REFERENCES:
patent: 4794561 (1988-12-01), Hsu
patent: 4890144 (1989-12-01), Teng et al.
patent: 5066607 (1991-11-01), Banerjee
patent: 5285093 (1994-02-01), Lage et al.
patent: 5448513 (1995-09-01), Hu et al.
patent: 5798965 (1998-08-01), Jun
patent: 6110798 (2000-08-01), Gonzalez et al.
patent: 6479370 (2002-11-01), Gonzalez et al.
patent: 6559032 (2003-05-01), Gonzalez et al.
patent: 6756293 (2004-06-01), Li et al.
patent: 6784076 (2004-08-01), Gonzalez et al.
patent: 6812150 (2004-11-01), Zheng
patent: 6861689 (2005-03-01), Burnett
patent: 6888200 (2005-05-01), Bhattacharyya
patent: 7045407 (2006-05-01), Keating et al.
patent: 7085153 (2006-08-01), Ferrant et al.
patent: 7112513 (2006-09-01), Smythe, III et al.
patent: 7433233 (2008-10-01), Chen et al.
patent: 2002/0110018 (2002-08-01), Ohsawa
patent: 2003/0190766 (2003-10-01), Gonzalez et al.
patent: 2004/0061148 (2004-04-01), Hsu
patent: 2005/0148147 (2005-07-01), Keating et al.
patent: 2005/0280113 (2005-12-01), Kim et al.
patent: 2006/0043456 (2006-03-01), Derderian et al.
patent: 2006/0125121 (2006-06-01), Ko et al.
patent: 2006/0146605 (2006-07-01), Bhattacharyya et al.
patent: 2007/0127289 (2007-06-01), Lee
patent: 0731972 (2001-11-01), None
patent: 1355358 (2003-10-01), None
patent: WO 95/15562 (1995-06-01), None
patent: WO 2004/044990 (2004-05-01), None
patent: 2004/102625 (2004-11-01), None
patent: WO 2005/114742 (2005-12-01), None
patent: WO 2006/026159 (2006-03-01), None
Morishita, et al., “A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI,” IEEE 2005 Custom Integrated Circuits Conference (2005), pp. 435-438.
International Search Report dated Jul. 4, 2008, for International Application No. PCT/US2008/054561 (5 pages).
Austrian Patent Office Search Report and Examination Report for SG Application No. 200905580-7, dated Jan. 5, 2010.

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