Capacitor layout technique for reduction of fixed pattern...

Details Capacitor layout technique for reduction of fixed pattern... Capacitor layout technique for reduction of fixed pattern...

2006-10-17

2006-10-17

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C257S535000

Reexamination Certificate

active

07124384

ABSTRACT:
A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by a first dielectric layer and a second dielectric layer. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first dielectric layer and the second dielectric layer. The two-layer conductive structure is an equal potential structure and includes a conductive coupling between the two layers.

REFERENCES:
patent: 5104822 (1992-04-01), Butler
patent: 5135883 (1992-08-01), Bae et al.
patent: 5220483 (1993-06-01), Scott
patent: 5225704 (1993-07-01), Wakamiya et al.
patent: 5548474 (1996-08-01), Chen et al.
patent: 5576925 (1996-11-01), Gorowitz et al.
patent: 5684315 (1997-11-01), Uchiyama et al.
patent: 5724107 (1998-03-01), Nishikawa et al.
patent: 6198153 (2001-03-01), Liu et al.

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