Capacitor in a dynamic random access memory

Details Capacitor in a dynamic random access memory Capacitor in a dynamic random access memory

1999-02-16

2001-01-23

Tran, Minh Loan (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S309000, C257S306000

Reexamination Certificate

active

06177700

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87121867, filed Dec. 30, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a dynamic random access memory (DRAM) capacitor.
2. Description of the Related Art
In IC fabrication, the primary goal is to make the resulting IC device as highly integrated as possible. To achieve this goal, the various semiconductor components in the IC device should be sized as small as possible in accordance with the design rules. In the case of DRAM, however, the downsizing of the device also reduces the size of its data storage capacitor, and hence reduces the capacitance of the capacitor, resulting in a reduced data-retaining capability by the capacitor. A DRAM capacitor with a smaller capacitance requires more frequent refreshing of the data stored therein, and thus is more power consumptive and less reliable to operate.
In general, the amount of stored charges within a DRAM capacitor must be above a certain threshold level so that the stored data can be retrieved correctly. When some of the dimensions of a DRAM capacitor are reduced, the maximum amount of stored charges capable of being stored by the capacitor drops correspondingly. Furthermore, as the charge-storing capacity of the capacitor drops, frequency of refreshes necessary for compensating the lost charges due to current leakage must be increased. Constant refreshes compromise the data processing speed of the DRAM. Hence, a method to reduce the area occupation of a capacitor on a semiconductor substrate without decreasing its storage capacity is one major issue for design engineers.
A two-dimensional, planar-type capacitor is used in an integrated circuit for a conventional DRAM that stores only a small amount of charge. The planar-type capacitor occupies a sizeable surface area on a substrate. Hence, the planar type capacitor is not suitable for a highly integrated DRAM. To achieve a highly integrated DRAM in the present state of technology, many 3-dimensional types of capacitors have been proposed to increase the capacitance of the DRAM capacitor, such as a stacked-type or a trench-type capacitor. However, the trench-type capacitor causes low yield rate and low reliability in DRAM production. Therefore, this invention provides a DRAM capacitor to increase surface area for the electrode to enhance the capacitance.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a DRAM capacitor. The capacitor has a concave shape to increase the surface area of the capacitor and enhance the amount of charge (capacitance) that can be stored on the capacitor. In addition, the refresh frequency is reduced and the integration of DRAM is increased.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a DRAM capacitor. A first dielectric layer is formed on a substrate having a gate and source/drain regions, a contact hole penetrating through the first dielectric layer is formed to expose the source/drain regions. The contact hole is filled with conductive material to form a basic structure of bottom electrode and a plug so that it can be electrically connected with the source/drain regions. A first spacer is formed on the basic structure of bottom electrode sidewalls, a second spacer is formed beside the first spacer. The top portion of the second spacer connects with that of the first spacer and be electrically connected with the basic structure of bottom electrode. A width of the second spacer gradually extends out from top portion to lower portion, and gradually has a separation from the first spacer. A dielectric layer is formed on the basic structure of bottom electrode, the first spacer and the second spacer. A conductive layer is formed on the dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5756388 (1998-05-01), Wu

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