Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-22
2001-11-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S396000, C438S239000, C438S238000
Reexamination Certificate
active
06323127
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a noble metal electrode and to a method of manufacturing the same. More particularly, the present invention relates to a method of fabricating a high-surface area (1 sq. micron or greater) noble metal electrode that can be employed as the bottom electrode of a capacitor.
BACKGROUND OF THE INVENTION
In the field of semiconductor memory devices such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM), it is known to employ capacitors containing noble metals such as Pt, Pd, Ir, and Ru as one of the electrodes and high-&egr; or ferroelectric materials as the dielectric. These materials provide a high-dielectric constant capacitor suitable for use in Gigabit memory applications.
Despite their importance in providing Gigabit memory devices, noble metals and high-&egr; or ferroelectric dielectrics have some problems associated therewith. Insofar as the noble metals are concerned, Pt, along with the other noble metals are difficult to pattern by conventional techniques such as reactive-ion etching (RIE) or wet chemical etching, especially at the deep sub-micron dimensions required for high density DRAM and FRAME. Alternative patterning Techniques using electrochemical deposition processes such as through-mask plating have been described in U.S. Pat. No. 5,789,320.
Recently, it has been reported that 10 nm Ta
2
O
5
films deposited on Pt electrodes could be produced with an oxide equivalent thickness of 0.9 nm and a leakage current density of less than 10 nA/cm
2
(sufficient to meet the requirements of future DRAMs), See, for example, “Structure and Electrical Properties of thin Ta
2
O
5
Deposited on Metal Electrodes, K. Kishiro, et al., Jap. J. Appl. Phys. 1, 37, 1336 (1998). However, in order to use Ta
2
O
5
and other high-e dielectrics or ferroelectric materials successfully in future memory devices, bottom electrode structures will need to have surface area of 1 sq. micron or greater in a very much smaller footprint. Without such enhanced-area electrodes, high density devices with the desired capacitance will require :dielectrics such as (Ba,Sr)TiO
3
(BST) which have lower oxide equivalent thicknesses, but are more challenging to integrate than Ta
2
O
5
.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a 3-dimensional capacitor structure with a high capacitance and a small footprint.
Another object of the present invention is to provide a method of fabricating a noble metal electrode that has a high-surface area, on the order of 1 sq micron or greater, associated therewith.
A further object of the present invention is to provide DRAM and FRAM storage devices which include at least the noble metal electrode of the present invention as a bottom electrode of a capacitor element.
These and other objects and advantages are achieved in the present invention by providing a cup-like, approximately cylindrical noble metal electrode with roughened inner and outer surfaces to provide additional surface area.
One aspect of the present invention thus relates to a method of fabricating a noble metal electrode having a surface area of about 1 sq. micron or greater. The method of fabricating the inventive noble metal electrode comprises the steps of:
(a) forming an electrode seed layer on a surface of a substrate;
(b) forming a silicon nitride layer on said electrode seed layer;
(c) forming a layer of silicon oxide on said silicon nitride layer;
(d) providing a patterned photoresist mask over said layer of silicon oxide and etching exposed portions of said silicon oxide until portions of said silicon nitride layer are exposed, and sidewalls of silicon oxide remain above the exposed silicon nitride layer to define spaces above said exposed silicon nitride layer;
(e) forming polysilicon sidewall spacers on said sidewalls;
(f) forming additional silicon oxide in said spaces whereby said spaces are completely filled;
(g) removing said polysilicon sidewall spacers to expose portions of said silicon nitride layer and to create annular channels having silicon oxide channel sidewalls;
(h) providing silicon nuclei on said channel sidewalls and oxidizing the nuclei to create a roughened channel wall surface;
(i) removing said silicon nitride layer at said channels to expose said seed layer;
(j) forming a noble metal layer in said channel to at least partially fill the same;
(k) removing said silicon oxide, said silicon nitride layer, and said seed layer external to said annular channels; and
(l) removing any remaining portions of said silicon oxide and silicon nitride interior to said annular channels to provide an electrode having a cylindrical shape and roughened inner and outer surfaces.
Further process steps can be included to the above processing steps in providing a capacitor that includes at least the inventive noble metal electrode as the bottom electrode of the capacitor structure.
Specifically, the capacitor structure is formed by first conducting steps (a)-(l) above and then the following steps are employed:
(m) forming a dielectric material layer about said electrode, said dielectric material is a high-&egr; or ferroelectric material; and
(n) forming a conductive material layer on said dielectric material layer.
Another aspect of the present invention relates to a noble metal electrode structure which comprises a patterned noble metal having a cylindrical shape, roughened inner and outer surfaces, and a surface area of at least 1 sq. micron or greater.
Further aspects of the present invention relate to a capacitor and a memory device, i.e., DRAM or FRAM, which include at least the high-surface area noble metal electrode of the present invention as a bottom electrode.
REFERENCES:
patent: 5342806 (1994-08-01), Asahina
patent: 5561082 (1996-10-01), Matsuo et al.
patent: 5565707 (1996-10-01), Colgan et al.
patent: 5633781 (1997-05-01), Saenger et al.
patent: 5789320 (1998-08-01), Andricacos et al.
patent: 5861331 (1999-01-01), Chien
patent: 5946566 (1999-08-01), Choi
Andricacos Panayotis
Costrini Gregory
Kotecki David Edward
Saenger Katherine Lynn
Capella, Esq. Steven
International Business Machines - Corporation
Luk Olivia
Niebling John F.
Scully Scott Murphy & Presser
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