Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-21
2002-12-24
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S306000, C257S309000, C257S310000, C257S758000
Reexamination Certificate
active
06498364
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to fabricating a capacitor for use in a semiconductor device, and more specifically, to a capacitor for integration with copper damascene processes and a method of manufacture therefore.
BACKGROUND OF THE INVENTION
Capacitors have gained wide acceptance and use in today's integrated circuit technology. As is well known, a common capacitor essentially comprises two conductive plates separated by an insulator. It is normal for the conductive plates to be made of aluminum and the insulator to be a dielectric material, such as silicon dioxide (SiO
2
).
Originally, capacitors were often placed upon a substrate of the integrated circuit (IC) and electrically connected to contact or via structures, as required by design. While these structures were quite effective, their presence caused a topographical aberration in the overlying dielectric material, such that the capacitor's structure would be reflected in the surface of the dielectric layer. As a result, special planarization techniques had to be performed to remove the aberration so that subsequent photolithographic processes were not adversely affected. The effect of the capacitor's aberrations in the photolithographic processes became even more acute as device sizes decreased.
Given the planarization problems associated with the earlier capacitor structures, the semiconductor manufacturing industry sought ways to form the capacitors while lessening their impact on the topography of the overlying dielectric layer. One such approach was to form the capacitor within a contact or via opening. This approach has worked very well for the larger submicron technologies. Because the capacitor was formed within the contact opening or via, its structure did not heavily influence the overlying dielectric layer. As such, the planarization problems present with previous capacitor structures were substantially reduced.
As the design rules have continued to decrease, however, difficulty has arisen with respect to forming a capacitor within these structures. Because smaller device size requires greater precision in the etching processes, the industry is moving toward an etching process known as damascene processing. Because the completed damascene structure has an upper cavity with a width larger than the lower cavity, a stair step topography results within the damascene opening. This damascene process provides more control when forming the trace openings, which in turn allows for manufacturing ICs in the submicron range.
The invention of the damascene process for forming trace openings allowed for the manufacture of ICs in the submicron range. However, because of the damascene's stair step topography, it has proven much more difficult to form capacitors within these damascene openings. One reason for this difficulty, stems from deposition problems that arise due to the deposition of the various layers needed for the capacitor, over the stair step topography. Because of the increased topography, the thickness of the layers that form the capacitor may vary significantly within the damascene structure. This variance in material thickness is difficult to control and makes it very difficult to achieve the desired degree of capacitance. Moreover, because of the number of layers that must be deposited within the smaller portion of the damascene structure, the material necessary to achieve the desired degree of conduction may not be adequately deposited within the damascene structure. Furthermore, voids may also be formed. Because of these uncertainties, the capacitor cannot be easily and consistently manufactured to the desired level.
Accordingly, what is needed in the art is a capacitor structure and a process for forming that capacitor structure that avoids the disadvantages associated with prior art structures and processes.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a capacitor for use in a semiconductor device having a damascene interconnect structure, such as a dual damascene interconnect, formed over a substrate of a semiconductor wafer. In one particularly advantageous embodiment, the capacitor, such as a metal-insulator-metal (MIM) capacitor, comprises a first capacitor electrode, such as copper, comprising a portion of the damascene interconnect structure. The capacitor further includes an insulator layer formed on the damascene interconnect structure wherein the insulator layer is a passivation layer, such as silicon nitride. The passivation layer may be an outermost or final passivation layer, or it may be an interlevel passivation layer within an integrated circuit. The capacitor further includes a second capacitor electrode comprised of a conductive layer, such as aluminum, that is formed on at least a portion of the insulator layer.
The material selected for the capacitor may vary. For example, in one embodiment, the insulator may be silicon nitride. However, in alternative embodiments, the insulator may be tantalum pentoxide. When using certain alternative embodiments, such as tantalum pentoxide with copper, it may be necessary to include an appropriate barrier layer to prevent migration of the copper into the surrounding dielectric.
In another aspect of the present invention, the semiconductor device includes a plurality of damascene interconnect structures that are electrically isolated from each other by a dielectric material. On any given layer on which the capacitor is to be formed, the passivation layer is formed on each of the plurality of interconnect structures.
In certain embodiments, the conductive layer is formed on at least two of the interconnect structures. Yet in another embodiment, the damascene interconnect is an outermost or final damascene interconnect structure, the insulator layer is an outermost capping layer and the second capacitor electrode comprises a portion of an outermost conductive layer formed on at least a portion of the insulator layer. This particular embodiment is particularly advantageous because the capacitor is formed on the outermost layers of the semiconductor wafer and the planarization problems that exist at prior levels are avoided. In such embodiments, the outermost layer may also be used to form a bond pad for the semiconductor device.
In yet another aspect, the present invention provides a semiconductor device formed on a substrate of a semiconductor wafer. This particular embodiment includes transistors formed over the substrate, damascene interconnect structures formed over and electrically connected to the transistors, an insulator passivation layer formed on one of the damascene interconnect structures, a conductive layer formed over one of the damascene interconnect structures, and the capacitor as previously described above, including the various embodiments.
A method of fabricating a capacitor for use in a semiconductor device having a damascene interconnect structure formed over a substrate of a semiconductor wafer is also provided. In this embodiment, the method includes forming a first capacitor electrode comprised of a portion of the damascene interconnect structure, forming an insulator layer formed on the damascene interconnect structure, wherein the insulator layer being a passivation layer, and forming a second capacitor electrode comprised of a conductive layer formed on at least a portion of the insulator layer.
The method embodiments also include steps of forming the variations of the devices as discussed above with respect to the capacitor. However, in those embodiments where the capacitor is formed on an interlevel dielectric, as opposed to the outermost dielectric level, the method further comprises planarizing the damascene interconnect structure prior to depositing the insulator material and further comprises planarizing a dielectric that is deposited over the capacitor once it is formed with a planarization process, such as chemical/mechanical planarization techniques.
The foregoing has outline
Downey Stephen
Harris Edward
Merchant Sailesh
Agere Systems Inc.
Fenty Jesse A.
Lee Eddie
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