Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-03-29
2001-11-27
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S306000, C257S915000
Reexamination Certificate
active
06323537
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuits and, more specifically, to an integrated circuit that includes a capacitor.
BACKGROUND OF THE INVENTION
Integrated circuits in general, and CMOS devices in particular, have continued to gain wide spread usage as user demands for increased functionality and enhanced benefits continue to increase. In order to meet this demand, the integrated circuit industry continues to decrease the feature size of circuit structures in order to place more circuits in the same size integrated circuit area thereby continuously increasing the packing density for a given chip size. Over the last several years, structures have evolved from 1.2 micron gate areas (1 Mbit capacity) in the past, down to gate structure areas of 0.25 microns (1 Gbit capacity) and are expected to become even smaller in the near future.
For example, the ever-increasing demand for computer memory to facilitate calculations and data storage has fostered intense development efforts in the area of Dynamic Random Access Memory (DRAM), and especially embedded DRAM. The DRAM is generally a collection of transistor devices with each having an integrated circuit capacitor typically connected to its source electrode thereby forming a memory cell. This collection of memory cells is then arranged into a memory structure using a word line and a bit line to address each memory cell. This integrated capacitor may store an electrical charge to represent a binary “1” or store no electrical charge for a binary “0” as instructed by the word and bit control lines.
Construction of these memory capacitors consists of using typically a tungsten (W) plug electrode structure for 0.25 micron technology connected to the source of the transistor, which then supports a dielectric material, such as tantalum pentoxide (Ta
2
O
5
), and then a top electrode, in sequence. There are many other uses for these capacitors in integrated circuits.
As the size technology of CMOS devices continues to shrink, the structure for a given memory size or circuit capability also shrinks as noted above. For example, the bond pads, which allow the integrated circuit to connect to external circuitry, cannot continue to shrink indefinitely. Currently, an integrated circuit package may have about 200 bond pads that are 50 microns by 50 microns in size. Shrinking topology coupled with this bond pad lower size limitation results in an excess of empty space around the bond pads. This allows for the inclusion of additional embedded memory around the bond pads. The use of higher dielectric constant oxides such as tantalum pentoxide as substitutes for silicon dioxide have allowed smaller structures still.
In an attempt to add the above-mentioned memory in certain conventional CMOS technologies, some manufacturers have partially etched back the material surrounding the plug to allow access to a portion of the area of the sidewalls in order to use the sidewalls of the plug to add to the capacitance per unit area. The capacitor dielectric then covers both the top of the plug, which is usually bare tungsten, and the sidewalls of the plug, which are usually titanium nitride (TiN). However, it has been observed that when this is done in conjunction with tantalum pentoxide being used as the dielectric, undesirable leakage current increases not in proportion to the area of the plug (a factor of two or three), but by two or three orders of magnitude. Accordingly, what is needed is a reduced feature size capacitor which overcomes the leakage current problems and other problems of the prior art.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit capacitor comprising a conductive plug comprising a top portion comprising sidewalls, and a bottom portion, wherein the bottom portion of the plug is coated with a material selected from the group consisting of titanium and titanium nitride and wherein the top portion of the plug is substantially not coated with a material selected from the group consisting of titanium and titanium nitride.
REFERENCES:
patent: 5442213 (1995-08-01), Okudaira et al.
patent: 5585673 (1996-12-01), Joshi et al.
patent: 5726497 (1998-03-01), Chao et al.
patent: 5811851 (1998-09-01), Nishioka et al.
patent: 5918118 (1999-06-01), Kim et al.
patent: 6001660 (1999-12-01), Park et al.
patent: 6218255 (2001-04-01), Fritzinger et al.
patent: 0 872 880 A2 (1998-10-01), None
patent: 3-292765 (1991-12-01), None
patent: 10-209399 A (1998-08-01), None
Applied Physics Letters, vol. 74, No. 24, Jun. 1999, Chang et al., “Thermal stability of Ta205 in metal-oxide-metal capacitor structures”, pp. 3705-3707, especially penultimate paragraph of p. 3707.
Fritzinger Larry Bruce
Layadi Nace
Merchant Sailesh Mansinh
Roy Pradip Kumar
Agere Systems Guardian Corp.
Prenty Mark V.
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