Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-13
2004-11-30
Mai, Anh Duy (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S297000, C257S300000
Reexamination Certificate
active
06825522
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to capacitor structures used in semiconductor devices and, in particular, relates to capacitor structures used to form memory cells in Dynamic Random Access Memory (DRAM) devices.
2. Description of the Related Art
The trend in the semiconductor processing industry has been to provide integrated circuits with increasingly higher circuit densities. Consequently, circuit components, such as capacitors and transistors, disposed within these integrated circuits are required to have reduced dimensions. However, because conventional circuit IS components having reduced dimensions are often unable to provide an acceptable performance, further improvements in circuit density requires the development of improved circuit components.
For example, a typical high density Dynamic Random Access Memory (DRAM) device may include an array of hundreds of millions of memory cells. Each memory cell usually includes a charge storage capacitor such that the state of charge of the capacitor determines the binary state of the memory cell. Essentially, the capacitor comprises an insulating material interposed between first and second conducting electrodes. Typically, the insulating material is a deposited dielectric material and one or both of the electrodes comprise doped semiconductor material such as doped polysilicon.
When a voltage difference, V, is applied between the electrodes of the capacitor, each electrode develops a charge, Q, according to the linear relationship Q=CV (1), wherein C is the capacitance of the capacitor. The typical capacitor has a capacitance that is approximately proportional to a function of the design parameters of the capacitor according to
C
∝
κ
A
d
(
2
)
,
wherein A is the area of each of the electrodes, d is the distance between the electrodes, and &kgr; is the dielectric constant of the insulating material. Furthermore, each charged capacitor discharges in an exponentially decaying manner with a decay constant, &tgr;, given by &tgr;=RC (3), wherein R is the resistance between the electrodes.
Because capacitors have a tendency to discharge relatively quickly, DRAM devices also incorporate refresh circuitry that periodically and selectively recharges the capacitors so as to enable the DRAM device to store information for extended periods of time. However, since memory cells cannot be accessed while they are being refreshed, it is desirable to extend the time between refresh cycles so as to provide the DRAM device with increased communication speeds. Thus, storage capacitors of DRAM devices are required to have a considerable capacitance so that they can effectively store charge for longer periods of time and, thus, require only a reasonably small refresh frequency.
However, because storage capacitors of higher density DRAM devices are confined within smaller spaces, it is becoming difficult to provide them with sufficient capacitance. Most notably, smaller capacitor size translates into smaller electrode area, A, which, according to (2), results in a decreased capacitance. To provide increased capacitance, one or both electrodes of the storage capacitors can be formed with a roughened surface, such as that which is provided by hemispherical grained (HSG) polysilicon, so as to increase the area over that which is provided by electrodes having planar surfaces. Other methods of providing increased capacitance involve using an insulating material having an increased dielectric constant and reducing the thickness of the dielectric insulating layer so as to reduce the distance between the electrodes.
However, as the distance between the electrodes is reduced, storage capacitors of DRAM devices are becoming more susceptible to the “depletion effect” such that the capacitance drops off in a voltage dependent manner. In particular, when mobile charge carriers are removed from the doped semiconductor electrode in response to an applied voltage, a depletion region substantially devoid of mobile charge carriers develops within the electrode. The depletion region begins at the interface adjacent the insulating layer and progressively extends into the electrode away from the insulating layer as more charge carriers are removed from the electrode. Because the net charge of the electrode is essentially comprised of ionized dopant atoms fixedly disposed throughout the depletion region, further enlargement of the depletion region as a result of further mobile charge carriers being removed from the electrode causes the geometric center of the electrode charge to be displaced away from the interface. Consequently, since the effect of the displacement of the geometric center of charge is identical to that of increasing the separation between the electrodes, i.e., an increase in the variable d in equation (2), the capacitance decreases as the applied voltage to the capacitor is increased.
Attempts have been made to reduce the depletion effect by increasing the doping concentration of the interface region of the electrode using conventional diffusion doping techniques. For example, an N-type polysilicon electrode is usually annealed in a phosphine (PH
3
) ambient so as to induce phosphorus atoms to diffuse into the electrode. The conditions of this process are chosen so that the doping concentration is greatest near the interface adjacent the insulating layer. However, the maximum achievable concentration is limited by the solid solubility limit of the polysilicon electrode and, if the electrode is exposed to increased temperatures in a subsequent processing step, it is likely that a substantial portion of the dopants will continue to diffuse so as to decrease the doping concentration adjacent the interface.
Thus, known doping methods are only able to provide the interface region of semiconductor electrodes with modest increases in doping concentration. Consequently, because capacitors having reduced sizes will be required in future generation DRAM devices, the problem of carrier depletion requires a more effective solution in order to satisfactorily address the issue of voltage dependent decreases in capacitance.
From the foregoing, therefore, it will be appreciated that there is a need for a miniaturized semiconductor-based capacitor having more stable operating characteristics. In particular, there is a need for the capacitor to have a relatively large capacitance that is more stable in response to a changing applied voltage. To this end, there is a need for the interface region of the semiconductor electrodes of the capacitor to have a greater concentration of doping atoms so as to reduce the effects of charge carrier depletion.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, the aforementioned needs are satisfied by a capacitor comprising a first conducting electrode having a richly doped interface layer. The first conducting electrode comprises a semiconductor bulk layer having a first surface and the interface layer extending from the first surface of the bulk layer. The interface layer comprises a plurality of dopant atoms chemically bonded thereto. The capacitor further comprises a second conducting electrode and an insulating layer interposed between the first and second conducting electrodes such that the insulating layer is disposed adjacent the interface layer of the first conducting electrode.
In another aspect of the invention, a method of forming a capacitor is provided. The method comprises forming a first conducting electrode having a bulk layer and an interface layer chemically bonded to the bulk layer, wherein the interface layer comprises a plurality of doping atoms chemically bonded thereto so as to reduce the extent of the depletion region of the first conducting electrode. The method further comprises forming an insulating layer adjacent the first conducting electrode such that the insulating layer is disposed adjacent the interface layer of the first conducting electrode. The method further comprises fo
DeBoer Scott J.
Powell Don C.
Duy Mai Anh
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
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