Capacitor dielectric structure of a DRAM cell and method for...

Details Capacitor dielectric structure of a DRAM cell and method for... Capacitor dielectric structure of a DRAM cell and method for...

2003-03-03

2004-12-28

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

C438S238000, C438S286000, C438S396000

Reexamination Certificate

active

06835630

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dielectric structure of a deep trench capacitor for a dynamic random access memory (DRAM) cell and, more particularly, to a SiN/SiON dielectric structure for improving capacitance and reducing leakage current and a method of forming thereof.
2. Description of the Related Art
There is much interest in reducing the size of individual semiconductor devices in order to increase their density on an integrated circuit (IC) chip, thereby reducing size and power consumption of the chip, and allowing faster operation. In order to achieve a memory cell with a minimum size, the gate length in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. However, the shorter gate length will result in higher leakage currents that cannot be tolerated, and the voltage on the bit line must therefore also be scaled down. This reduces the charges stored on a storage capacitor, and thus requires a larger capacitance to ensure that stored charges are sensed correctly. Recently, in fabricating highly-integrated memory devices, such as dynamic random access memory (DRAM), a deep trench capacitor has been developed within a silicon substrate without consuming any additional wafer area.
In order to prolong the data retention time, the capacitance of the storage capacitor must be increased by increasing the capacitor area, decreasing the effective dielectric thickness between the capacitor plates, or increasing the dielectric constant (k) of the capacitor dielectric. However, increasing the capacitor area conflicts with the need to shrink the memory cell, and reducing the dielectric thickness is difficult because the dielectric thickness has already been reduced to a practical minimum. Therefore, improving the capacitor dielectric with a high dielectric constant is a way to provide adequate capacitance in view of shrinking cell size.
Conventionally, the most prominent material used to from the capacitor dielectric is Ta
2
O or Al
2
O
3
that facilitates the refining process for making a thinner layer, but fails in high-k dielectric application. Accordingly, various multilayered structures including oxide and nitride, such as SiO
2
/SiN/SiO
2
, SiN/SiO
2
and SiN/SiO
2
/SiON, have been developed for forming the capacitor dielectric.
FIG. 1
is a sectional diagram showing a conventional deep trench capacitor. A DRAM cell comprises a transistor
22
and a deep trench capacitor
20
having a bottom electrode plate
14
, a capacitor dielectric
16
and an upper electrode plate
18
. The bottom electrode plate
14
can be formed from the n
+
-doped region in a silicon substrate
10
surrounding a deep trench
12
or from a doped-polysilicon layer that conformally covers the sidewall and the bottom of the deep trench
12
. The upper electrode plate
18
is formed by filling the deep trench
12
with a conductive layer.
FIG. 2A
is a conventional SiO
2
/SiN/SiO
2
dielectric structure served as the capacitor dielectric
16
. A multi-layered SiO
2
/SiN/SiO
2
structure, called an ONO structure, has been employed as the capacitor dielectric
16
. Because the SiN dielectric constant (k=7.6) is 1.5~2 times larger than that of the SiO
2
dielectric constant (k=3.9), the SiN layer in the ONO structure can increase the capacitance of the deep trench capacitor. The SiO
2
layer in the ONO structure is employed to repair the damaged interface. Nevertheless, the critical thickness of the ONO structure has a limitation of 5~10 nm, the dielectric constant of the ONO structure only reaches approximately 7, and problems of difficult process, low yield, high process cost, and leakage current occur.
FIG. 2B
is a conventional SiN/SiO
2
dielectric structure served as the capacitor dielectric
16
. A stacked SiN/SiO
2
structure, called a NO structure, has been employed to form the capacitor dielectric
16
. The NO structure comprises a SiN liner deposited ion the sidewall and bottom of the deep trench
12
by low pressure vapor deposition (LPCVD) and a thin SiO
2
layer grown on the SiN liner by re-oxidation process. In the NO structure, the SiN liner with a dielectric constant 1.5~2 times larger than the dielectric constant of the thin SiO
2
layer, the thickness of the SiN liner is 40~80 Å and the thickness of the SiO
2
layer is 3 nm. Thus, the capacitance of the deep trench capacitor is effectively increased. However, there is still a problem of leakage current caused by the SiN liner. Also, during deposition of the SiN liner, the process gases, such as SiH
4
and NH
3
, cause pinhole structure defects in the SiN liner. Although the SiO
2
layer grown on the SiN liner can repair the defects, decrease the pinhole density and reduce leakage current to achieve a preferred distribution of breakdown voltage, the SiN liner is too thin to increase the dielectric constant of the NO structure.
FIG. 2C
is a conventional SiN/SiO
2
/SiON dielectric structure served as the capacitor dielectric
16
. A stacked SiN/SiO
2
/SiON structure has been employed to form the capacitor dielectric
16
, in which a post oxidation annealing with NH
3
is employed on the above-described NO structure to form a SiON layer on the SiO
2
layer. The SION layer contributes a higher dielectric constant to the capacitor dielectric
16
, resulting in a significantly improved capacitance. However, the stacked SiN/SiO
2
/SiON structure suffers from remarkably leakage current due to the usage of hydrogen-containing gas, such as NH
3
, in the formation of the SiON layer.
SUMMARY OF THE INVENTION
The present invention provides a SiN/SiON dielectric structure of a capacitor for a DRAM cell to increase dielectric constant and decrease leakage current, thus ensures the electrical reliability of the capacitor dielectric structure.
Accordingly, a semiconductor silicon substrate is provided with a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N
2
O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.
It is a principle object of the invention to provide a capacitor dielectric structure and a method of forming the same that may be applied to the formation of a deep trench capacitor or a stacked capacitor in DRAM.
It is another object of the invention to provide a SiON layer on a SiN layer to increase the dielectric constant of the capacitor dielectric structure.
Yet another object of the invention is to provide wet oxidation with N
2
O as the reactive gas to form a SiON layer on a SiN layer to reduce leakage current.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.


REFERENCES:
patent: 5618745 (1997-04-01), Kita
patent: 6346487 (2002-02-01), Buchanan et al.
patent: 6444592 (2002-09-01), Ballantine et al.
patent: 6607965 (2003-08-01), Moradi et al.
patent: 6630384 (2003-10-01), Sun et al.
patent: 2000-183055 (2000-06-01), None
patent: 440969 (1988-06-01), None

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