Capacitor constructions

Details Capacitor constructions Capacitor constructions

2001-05-11

2002-08-13

Dinkins, Anthony (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S311000, C361S306300

Reexamination Certificate

active

06433994

ABSTRACT:

TECHNICAL FIELD
The invention pertains to capacitor constructions, methods of forming bitlines, and to methods of forming structures comprising both capacitors and bitlines.
BACKGROUND OF THE INVENTION
A typical semiconductor dynamic random access memory (DRAM) array will comprise wordlines, bitlines, and capacitor structures. A prior art method of forming a portion of a memory array is described with reference to
FIGS. 1-6
.
Referring initially to
FIG. 1
, a semiconductor wafer fragment
10
comprises a semiconductive material substrate
12
having a first insulative material
14
formed thereover. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Substrate
12
can, for example, comprise a monocrystalline silicon wafer having various circuitry elements (not shown) associated therewith. Insulative material
14
can comprise, for example, borophosphosilicate glass (BPSG).
Conductive plugs
16
are formed to extend through insulative material
14
and to substrate
12
. Conductive plugs
16
can comprise any of a number of conductive materials, including, for example, metals and/or conductively doped polysilicon. Conductive plugs
16
can be electrically connected with conductive circuitry that is part of substrate
12
, and which is not shown. Plugs
16
can be formed within insulative material
14
by, for example, etching openings in material
14
, filling such openings with the conductive material, and subsequently removing any excess conductive material remaining over insulative material
14
by, for example, chemical-mechanical polishing.
A second insulative material
18
is formed over conductive plugs
16
and first insulative material
14
. Second insulative material
18
can comprise, for example, silicon dioxide.
A plurality of patterned bitlines
20
,
22
and
24
are formed over second insulative material
18
. The patterned bitline constructions
20
,
22
and
24
comprise a pair of conductive materials
26
and
28
, and a third insulative material
30
overlying conductive materials
26
and
28
. Conductive materials
26
and
28
can comprise, for example, conductively doped polysilicon and a metal-silicide, respectively. The metal-silicide can comprise, for example, titanium silicide or tungsten silicide. It is noted that although the shown bitlines comprise two conductive materials, the bitlines can also be formed to comprise only one conductive material, or more than two conductive materials. If the bitlines comprise only one conductive material, such conductive material can be either conductively doped polysilicon or a metal silicide. The insulative material
30
of bitline constructions
20
,
22
and
24
can comprise one or more insulative layers. Individual layers can comprise, for example, silicon dioxide.
A plurality of insulative spacers
32
are formed along sidewalls of bitline constructions
20
,
22
and
24
. Insulative spacers
32
can comprise, for example, silicon nitride.
FIG. 2
shows a top view of fragment
10
at the processing step of
FIG. 1
, and shows bitline constructions
20
,
22
and
24
extending as lines across an upper surface of second insulative material
18
.
FIG. 2
also shows wordline locations
34
,
36
and
38
(indicated by dashed lines) extending across fragment
10
perpendicularly relative to bitline structures
20
,
22
and
24
. Wordlines can be formed in locations
34
,
36
and
38
to extend either above or below bitline structures
20
,
22
and
24
, and accordingly can be formed either before or after the patterning described with reference to FIG.
1
.
Referring next to
FIG. 3
, wafer fragment
10
is shown in a view corresponding to that of
FIG. 1
, and at a processing step subsequent to FIG.
1
. Specifically, a fourth insulative material
40
has been formed over bitline constructions
20
,
22
and
24
, and a patterned masking layer
42
has been formed over fourth insulative material
40
. Fourth insulative material
40
can comprise, for example, a silicon oxide such as, for Example, silicon dioxide or BPSG, and patterned masking layer
42
can comprise, for example, photoresist.
Patterned masking layer
42
has openings
44
extending therein and such openings are transferred through insulative materials
40
and
18
with a suitable etch to extend the openings to conductive plugs
16
. Preferably, the etch utilized to extend openings
44
through insulative materials
40
and
18
is an etch selective for materials
40
and
18
relative to spacers
32
. However, a difficulty with the etch can be that the etch is not 100% selective for the silicon oxide materials relative to the silicon nitride material, and accordingly if the etch is conducted too long it can etch through the silicon nitride spacers to expose conductive materials
26
and
28
. The shown embodiment of
FIG. 3
is an idealized etch wherein only insulative materials
18
and
40
have been etched, and wherein spacers
32
have not been etched. It is to be understood that such idealized etch rarely, if ever occurs, and accordingly there is typically at least some etching of insulative spacers
32
during the etch of materials
18
and
40
.
FIG. 4
shows a top view of wafer fragment
10
at the processing step of
FIG. 3
, and shows that openings
44
are preferably formed at locations between bitlines
20
,
22
and
24
(shown in phantom), as well as between wordline locations
34
,
36
and
38
. The processing of
FIG. 4
is shown as idealized processing wherein the openings
44
are aligned to be between bitlines
20
,
22
and
24
. It is noted that occasionally mask S misalignment occurs, and openings
44
are accordingly shifted to extend into one or more of bitline constructions
20
,
22
and
24
. Such shift can result in exposure of conductive materials
28
and/or
26
during the etch utilized to form openings
44
. Such exposure of conductive materials
28
and/or
26
can ultimately result in device failure.
FIG. 5
shows wafer fragment
10
at a processing step subsequent to that of
FIG. 3
, and in a view corresponding to that of FIG.
3
. Capacitor constructions
46
and
48
are formed between and over bitline constructions
20
,
22
and
24
, and in electrical connection with conductive plugs
16
. Capacitor constructions
46
and
48
comprise conductive storage nodes
50
and
52
, respectively. Conductive storage nodes
50
and
52
can be formed of, for example, metal and/or conductively doped polysilicon. Capacitor constructions
46
and
48
further comprise a dielectric layer
54
and a conductive capacitor plate
56
. Dielectric layer
54
can comprise, for example, silicon dioxide, silicon nitride, tantalum pentoxide, and/or other insulative materials known to persons of skill in the art. Conductive capacitor plate
56
can comprise, for example, metal and/or conductively doped polysilicon.
FIG. 6
shows a top view of wafer fragment
10
at the processing step of
FIG. 5
, and shows additional capacitor constructions
58
and
60
associated with wafer fragment
10
. Constructions
58
and
60
can be similar to constructions
46
and
48
in comprising storage nodes (not shown), dielectric layer
54
, and conductive capacitor plate
56
. In the shown embodiment, capacitor constructions
46
,
48
,
58
and
60
extend over wordline locations
34
,
36
and
38
, as well as over bitlines
20
,
22
and
24
. Capacitor constructions
46
,
48
,
58
and
60
are typically electrically connected to transistor gates associated with wordlines
34
,
36
and
38
, as well as t

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