Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-09-05
2001-06-05
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S536000, C438S011000, C438S014000, C438S015000, C438S018000, C324S756010, C324S762010
Reexamination Certificate
active
06242757
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of integrated circuit manufacture with particular reference to alignment between masks.
BACKGROUND OF THE INVENTION
Integrated circuits are formed by laying down multiple layers of various materials including conductors, semiconductors, and dielectrics. In most cases, any given layer is etched through a suitable mask (generally a contact mask of photoresist) before the next layer is deposited. Since the different layers of the integrated circuit form a unified whole, it is clear that the pattern into which a newly deposited layer is formed must be carefully aligned with respect to the pattern already present in the layer below.
A number of techniques have been developed for effecting layer to layer alignment quickly and accurately. In all cases, some sort of alignment mark is provided in the upper pattern and this must line up in the correct fashion with respect to an alignment mark already present in the lower pattern. This is most readily accomplished by observation under a microscope but, for manufacturing purposes, this is method too slow. Alignment is therefore performed by use of machines that, once set up, can be depended upon to continue to provide good alignment.
No machines are perfect so it is necessary to be able to check, quickly and accurately with minimum process disruption, on how good the actual alignment is at any particular point in time between any two masks. When the two patterns whose alignment is to be checked are both made of conductive material and the two layers will be in contact with one another, the approach described by D. S. Perloff in Solid state electronics Aug. 21, 1978—“A Van der Pauw structure for determining mask superposition errors on semiconductor slice” has been generally used.
Perloff's structure is illustrated in
FIG. 1. A
metallic square
10
is etched out of the lower metal layer and includes contact arms
1
through
4
. After the second layer has been laid down, a set of contacting plates
5
-
8
is etched out of it as part of the upper pattern. If the alignment between the two layers is correct, then the resistance measured between the various upper and lower contacting points should be symmetrical. For example, R
45
should be the same as R
35
if contact plate
5
is exactly midway between
3
and
4
. Should some horizontal misalignment have occurred, then plate
5
will be closer to
3
than to
4
(or vice versa) and differences in the two resistance readings will be seen. Similar considerations apply to vertical misalignment. This description is over-simplified but the basic requirement that the two patterned layers must be in contact with each other is always present.
It is, however, sometimes the case that there is a layer of a dielectric material between the two conductive materials. Clearly, in such a case, the Perloff approach is not applicable. The present invention offers a solution to this problem.
A routine search of the prior art was made but all the references that were identified were found to be variations on and improvements of the basic Perloff method discussed above. For example, Ausschnitt (U.S. Pat. No. 4,538,105) uses four rather than two conductors, but the principle is the same. Allen et al. (U.S. Pat. No. 5,699,282) uses a reference test structure to improve the quality of the measurements. Cresswell et al. (U.S. Pat. No. 5,617,340) also describe the use of reference standards while Henderson et al. (U.S. Pat. No. 4,647,850) use a U-shaped structure with a contacting bar that does not touch the arms of the U when alignment is correct. Thus, the prior art has not, to our knowledge, provided a solution to the problem of aligning patterns of conductive material that are separated by a dielectric layer.
SUMMARY OF THE INVENTION
It has been a object of the present invention to provide a structure suitable for aligning two patterns formed in two conductive layers separated by a dielectric layer.
Another object of the invention has been to provide a process for manufacturing said structure together with a method for utilizing it during alignment.
A further object of the invention has been that said method be suitable for automating.
These objects have been achieved by including in the lower pattern a square and, as part of the upper pattern, four T-shaped capacitor electrodes. The latter are positioned so that, when the alignment is exact, they all overlap the square by the same amount. Thus, under conditions of exact alignment, the capacitance value measured between any one of the top electrodes and the square will be the same for all. When, however, misalignment occurs, the degree of overlap will change, increasing on one side of the square while decreasing at the opposite side. In this way a comparison of measured capacitance values between electrodes located on opposing sides of the square will indicate whether, and what extent, misalignment has occurred.
REFERENCES:
patent: 4538105 (1985-08-01), Ausschnitt
patent: 4647850 (1987-03-01), Henderson et al.
patent: 5617340 (1997-04-01), Cresswell et al.
patent: 5699282 (1997-12-01), Allen et al.
patent: 6143621 (2000-11-01), Tzeng et al.
patent: 6144040 (2000-11-01), Ashton
patent: 6153892 (2000-11-01), Ohsono
patent: 6172513 (2001-01-01), Contrata
patent: 4-32216 (1992-02-01), None
D.S.Perloff, “A Van Der Pauw Resistor Structure for Determining Mask superposition errors on semiconductor slices” in Solid State Electronics, Aug. 21, 1978, vol. 21, pp. 1013-1-18.*
D.S. Perloff in Solid State Electronics Aug. 21, 1978, “A Van der Pauw Structure for Determining Mask Superposition Errors on Semiconductor Slice,” pp. 1013-1018.
Chung Wen-Jye
Tzeng Kuo-Chyuan
Ackerman Stephen B.
Kang Donghee
Saile George O.
Taiwan Semiconductor Manufacturing Company
Thomas Tom
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