Capacitor and conductive line constructions

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257309, 257296, H01L 31119

Patent

active

061147206

ABSTRACT:
A semiconductor processing method of forming a capacitor construction includes, a) providing a pair of electrically conductive lines having respective electrically insulated outermost surfaces; b) providing a pair of sidewall spacers laterally outward of each of the pair of conductive lines; c) etching material over the pair of conductive lines between the respective pairs of sidewall spacers selectively relative to the sidewall spacers to form respective recesses over the pair of conductive lines relative to the sidewall spacers, the etching leaving the outermost conductive line surfaces electrically insulated; d) providing a node to which electrical connection to a capacitor is to be made between the pair of conductive lines, one sidewall spacer of each pair of sidewall spacers being closer to the node than the other sidewall spacer of each pair; e) providing an electrically conductive first capacitor plate layer over the node, the one sidewall spacers, and within the respective recesses; and f) providing a capacitor dielectric layer and a second capacitor plate layer over the first capacitor plate layer. In another aspect, a semiconductor processing method of processing relative to a conductive line includes, i) providing a pair of sidewall spacers laterally outward of an electrically conductive line; and ii) etching material over the conductive line between the sidewall spacers selectively relative to the sidewall spacers to form a recess over the conductive line relative to the sidewall spacers. Capacitor and conductive line constructions produced according to the above and other methods are also disclosed.

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