Capacitor

Details Capacitor Capacitor

2000-08-07

2004-10-12

Nguyen, Cuong (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S296000

Reexamination Certificate

active

06803640

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor device and a fabricating method therefor, and more particularly to a capacitor and a fabricating method therefor in an manner that prevents the occurrence of lifting between a polysilicon pattern and a blocking metal layer of an upper electrode in the process of a wire-bond attached chip capacitor (hereinafter referred to as WACC).
2. Description of the Prior Art
A wire-bond attached chip capacitor (WACC) is mounted to an integrated circuit (IC), or chip, for enhancement of stable operation. The WACC is coupled to the IC by wire-bonding pads respectively positioned between the IC components and the WACC.
Generally, the WACC has been widely deployed in the power supply of semiconductor devices and other electronic devices.
FIGS. 1
a
through
1
d
are diagrams for illustrating sequential processes of a conventional WACC fabrication method. With reference to the drawings, the method for fabricating the conventional WACC will now be described in detail.
As shown in
FIG. 1
a
, a first insulating layer
12
of an oxide layer is formed on a p++ type silicon substrate
10
. The first insulating layer
12
is selectively etched to expose an active area of the substrate
10
. Accordingly, the substrate
10
of the active area positioned at the upper electrode is selectively etched to a predetermined thickness to form a plurality of trenches (t) in the substrate
10
.
As shown in
FIG. 1
b
, an oxide-nitride-oxide (ONO) dielectric layer
14
is formed on the resultant structure of
FIG. 1
a
. A polysilicon layer
16
is constructed in a deposition structure comprising an undoped polysilicon layer
16
a
below a doped polysilicon layer
16
b
(referred to herein as an “undoped/doped” structure) formed over the dielectric layer
14
. At this time, the undoped polysilicon layer
16
a
is formed at a thickness of 500 Angstroms (hereinafter referred to as A) at 620° C., while the doped polysilicon layer
16
b
is formed at a thickness of 2500 A at 540° C. The purpose of the ‘undoped/doped’ doubly layered structure in the polysilicon layer
16
is because the trenches t are formed for fabricating a capacitor to increase its effective area in designing a semiconductor device in accordance with a design rule of less than 0.25 &mgr;m. Relying on solely the application of a general impurity impregnation process, it would be difficult to impregnate enough impurity to the upper end of the polysilicon layer
16
.
As shown in
FIG. 1
c
, the polysilicon layer
16
is removed, save the region of the upper electrode forming portion, so as to form a polysilicon pattern
16
′. In the aforementioned process, the top oxide layer of the ONO dielectric layer
14
is also removed, causing thinning of the resultant dielectric layer
14
. Accordingly, any remaining dielectric layer
14
remaining beyond the portion covered by the polysilicon pattern
16
′ is eliminated. In order to make an ohmic contact between a blocking metal layer (a layer to be deposited during the next step) and the active area, p+ type impurity
24
is ion-impregnated in blanket onto the structure. As a result, a p+ type impurity diffusion area
18
is formed in the substrate
10
in the active region positioned at one side of the polysilicon pattern
16
′.
As shown in
FIG. 1
d
, the blocking metal layer is formed and annealed over the surface constructed by the previous processes, and an aluminum layer is, then, formed thereon. As a result, a first metal layer of a “blocking metal layer/aluminum layer” deposition structure is formed. For example, the blocking layer may comprise a “Ti/TiN” deposition structure, wherein Ti is formed in thickness of 150 A and TiN is formed in thickness of 1000 A. The Ti of the blocking metal layer forms a silicide layer by reacting with the lower silicon (named for the combination of the polysilicon pattern and p++ type silicon substrate) in the annealing process, so as to improve adhesion between the blocking metal layer and silicon. TiN of the blocking metal layer prevents diffusion of the aluminum layer into the silicon in the deposition of the first metal layer. Accordingly, the first metal layer is selectively etched to expose a predetermined part of the first insulating layer
12
, thereby respectively forming a first metal pattern
20
a
to be connected with the polysilicon pattern
16
′ and a first metal pattern
20
b
to be connected with the p+ type impurity diffusion area
18
. Then, a second insulating layer
22
made of an oxide layer as inter-layer insulating material is formed on the first insulating layer
12
that includes the first metal patterns
20
a
,
20
b
. A via hole (h) is then formed by selectively etching the second insulating layer
22
to expose a predetermined portion of the first metal pattern
20
b
connected with the p+ type impurity diffusion area
18
. Finally, the second metal pattern
24
is formed on the second insulating layer
22
that includes the via hole (h), thereby completing the fabrication process.
As shown in
FIG. 1
d
, a WACC is thus fabricated in the structure having an upper electrode (I) on its top portion, in which the polysilicon pattern
16
′ and the first metal pattern
20
a
are connected with the dielectric layer
14
positioned therebetween, and a lower electrode (II) on its bottom portion, in which the first metal pattern
20
b
and the second metal pattern
24
are connected with the p++ type substrate
10
.
As a consequence of the above process, however, the fabricated WACC suffers from a number of limitations. For example, adhesion between the silicon and the upper blocking metal layer is determined by the degree to which the Ti and silicon react during the annealing process. The thickness of the resultant layer (for example the silicide layer) is generally known to be inversely proportional to the doping level of the lower silicon layer. In other words, if the impurity doping level of the lower silicon is high, the reacted layer becomes thinner. If the impurity doping level of the lower silicon is low, the reacted layer becomes thicker. In this configuration, the lower silicon layer indicates all of the polysilicon pattern
16
′ and the p++ type substrate
10
.
Thus, in order to improve adhesion between Ti and silicon, the thickness of the reacted layer should be higher than a predetermined level thereof by lowering the impurity doping level of the lower silicon.
However, when the WACC is fabricated according to the aforementioned processes, the polysilicon layer is constructed in the “undoped/doped” double deposition structure. As a result, in addition to the high doping level of the polysilicon layer, the impurity doping level of the polysilicon pattern
16
′ becomes much higher by the blanket ion-impregnation of p+ type impurity, which has been additionally formed to make an ohmic contact. For this reason, the silicide layer is marginally formed between the polysilicon pattern
16
′ and the blocking metal layer. As a consequence, a problem arises in that adhesion between the polysilicon pattern
16
′ and the blocking metal layer of the upper electrode becomes weak, thereby resulting in the phenomenon of lifting therebetween.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to address the aforementioned limitations by providing a WACC having an upper electrode with its polysilicon layer constructed in a triply-layered deposition structure of “undoped/doped/undoped polysilicon layers” to enable the polysilicon layer contacting the blocking metal layer to be the undoped polysilicon layer. In this manner, an effective suicide layer is formed between the polysilicon layer and the blocking metal layer to reinforce adhesion and prevent occurrence of lifting therebetween.
It is another object of the present invention to provide a method for fabricating a capacitor that helps to effectively produce the se

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