Electronic digital logic circuitry – Interface
Reexamination Certificate
2002-01-04
2003-02-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
C326S082000, C326S022000
Reexamination Certificate
active
06515512
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to signal re-referencing, and more particularly to logic level re-referencing for digital signals in automatic test systems.
BACKGROUND OF THE INVENTION
Communicating among different portions of a test system customarily involves the use of level translators to re-reference digital signals.
FIG. 1
illustrates a conventional technique for conveying digital signals between a first portion
110
and a second portion
112
of a test system. The first and second circuit portions
110
,
112
may be physically distant from each other, or they may operate from different power supplies or grounds. Level translators
122
and
124
are connected between the first and second circuit portions
110
and
112
. Each level translator receives an input signal from one circuit portion (e.g., from driver
114
or driver
120
) and provides a re-referenced output signal to the other circuit portion (e.g., to receiver
116
or
118
). Each level translator
122
,
124
also receives power and ground from both of the circuits portions
110
and
112
.
The purpose of a level translator is to transform an input signal having one set of logic levels into an output signal having another set of logic levels. For example, assume that a digital signal is to be conveyed from TTL logic levels to ECL logic levels. As is known, TTL logic generally uses +5 v and ground for powering digital logic, and ECL logic generally uses ground and −5.2 v. Logic high and low levels are approximately 4 v and 1 v, respectively, for TTL, but are approximately −0.8 v and −1.8 v for ECL. To convey logic signals from TTL to ECL, a level translator respectively transforms high and low logic signals on the TTL side into high and low logic signals on the ECL side.
By applying level translators
122
,
124
to the system of
FIG. 1
, the different portions
110
and
112
of the test system can communicate with each other. They communicate, however, at the expense of increased component count and increased complexity.
When conveying large numbers of signals, such as data or address busses, level translators constitute a significant portion of an overall system design. Level translators take up space that could otherwise be used for performing more substantive operations. They also consume power and cost money. In addition, when level translators are used to transmit signals that have precise timing relationships to one another, it becomes difficult to maintain equal path delays among the different signals. Circuit board layout becomes particularly complicated.
To overcome the expense and complexity of providing separate level translators, many circuit designs have incorporated level translators within integrated circuits. The level translators then reside within the same physical packages that house the devices that receive the level-translated signals. But because conventional level translators require power and ground connections from both of the circuit portions to which they connect (e.g., circuit portions
110
and
112
), the number of power and ground leads that must be provided on the integrated circuit packages grows considerably. The proliferation of power and ground leads reduces the number of leads that are available for conveying other signals, potentially limiting the functional capabilities of the integrated circuits.
What is needed is a way of conveying digital logic signals with less complexity. In particular, what is needed is a way of conveying digital logic between different portions of a system without having to convey as many power and ground connections as are required using current techniques.
SUMMARY OF THE INVENTION
With the foregoing background in mind, it is an object of the invention to convey digital logic between different portions of a system or between different logic families.
To achieve the foregoing objects and other objectives and advantages, a logic level re-referencing circuit for re-referencing a digital input signal from a first logic environment to a second logic environment includes a non-inverting circuit having an input and an output, and a non-inverting transfer characteristic between the input and the output. The logic level re-referencing circuit includes a capacitive element having a first node coupled to the input of the non-inverting circuit and a second node arranged to receive the digital input signal. A resistive element is coupled between the input and the output of the non-inverting circuit. Rising and falling edges of the digital input signal couple through the capacitive element to the input of the non-inverting circuit, where they activate the non-inverting circuit to respectively assume high and low digital logic states. Output states are maintained by feedback through the resistive element. To correct for transients between the DC levels of the first and second logic environments, the re-referencing circuit includes a transient correcting circuit. The transient correcting circuit has a first input coupled to a substantially DC level of the first logic environment, a second input coupled to a substantially DC level of the second logic environment, and an output coupled to the input of the non-inverting circuit. The transient correcting circuit applies transient differences between the two environments to cancel the effects of transients in the digital input signal.
REFERENCES:
patent: 4255712 (1981-03-01), Petrie
patent: 4794283 (1988-12-01), Allen et al.
patent: 5414354 (1995-05-01), Bushman et al.
patent: 6031404 (2000-02-01), Roither et al.
patent: 02241355 (1990-09-01), None
Cho James H.
Rubenstein Bruce D.
Teradyne, Inc.
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