Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-04
2003-07-22
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S309000, C257S310000, C257S532000
Reexamination Certificate
active
06597028
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric random access memory and more particularly, to a capacitively coupled ferroelectric random access memory cell and a method for manufacturing the same.
2. Discussion of the Related Art
FRAM (ferroelectric random access memory) is a type of non-volatile read/write random access semiconductor memory. FRAM combines the advantages of SRAM (static random access memory) with its fast writing speed, and EAROM (electrically alterable read-only memory) with its non-volatility and in-circuit programmability.
A ferroelectric memory cell consists of a ferroelectric capacitor and a transistor. The properties of a dielectric material in the FRAM provide special advantages. The dielectric material has a high dielectric constant and can be polarized by an electric field. The polarization remains until it is reversed by an opposite electrical field. This makes the memory non-volatile.
A goal in designing a non-volatile ferroelectric random access memory is to realize a small die and high speed read/write at low supply voltage.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an improved ferroelectric random access memory.
An object of the present invention is to provide a ferroelectric random access memory cell including a ferroelectric capacitor having fast switching speeds.
Another object of the present invention is to provide a ferroelectric capacitor with a high charge storage capability.
Another object of the present invention is to provide a ferroelectric capacitor that has low leakage current and relatively linear capacitance dependence on voltage.
Another object of the present invention is to provide a simplifier manufacturing process of a ferroelectric random access memory cell.
Another object of the present invention is to provide a ferroelectric memory cell including a ferroelectric capacitor that is driven by capacitive coupling.
Additional features and advantages of the invention will be set forth in the description, which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a ferroelectric memory cell includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, a high permittivity dielectric layer formed over the ferroelectric capacitor, wherein the high permittivity dielectric layer includes an encapsulation layer and completely covers the top electrode, and a local interconnect electrode formed on the encapsulation layer.
In another aspect of the present invention, an integrated circuit includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, a high permittivity dielectric layer formed over the ferroelectric capacitor, wherein the high permittivity dielectric layer includes an encapsulation layer and completely covers the top electrode, and a local interconnect electrode formed on the encapsulation layer.
In another aspect of the present invention, a method for forming an integrated circuit includes forming a ferroelectric capacitor, wherein the ferroelectric capacitor includes a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, forming a high permittivity dielectric layer over the ferroelectric capacitor, wherein the high permittivity dielectric layer includes an encapsulation layer and completely covers the top electrode, and forming a local interconnect electrode on the encapsulation layer so that the top electrode, the encapsulation layer and the local interconnect electrode form a second capacitor.
In another aspect of the present invention, a ferroelectric memory cell includes a conductive barrier, a ferroelectric capacitor formed on the conductive barrier, wherein the ferroelectric capacitor includes a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, and a high permittivity dielectric layer formed between the conductive barrier and the ferroelectric capacitor, wherein the conductive barrier connects the ferroelectric capacitor to an underlying device through a connecting electrode formed directly below the ferroelectric capacitor.
In another aspect of the present invention, an integrated circuit includes a conductive barrier, a ferroelectric capacitor formed on the conductive barrier, wherein the ferroelectric capacitor includes a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, and a high permittivity dielectric layer formed between the conductive barrier and the ferroelectric capacitor, wherein the conductive barrier connects the ferroelectric capacitor to an underlying device through a connecting electrode formed directly below the ferroelectric capacitor.
In another aspect of the present invention, a method for forming an integrated circuit includes forming a conductor, forming a conductive barrier on the conductor, forming a high permittivity dielectric layer on the conductive barrier, and forming a ferroelectric capacitor on the high permittivity dielectric layer, wherein the ferroelectric capacitor includes a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, wherein the conductive barrier connects the ferroelectric capacitor to an underlying device through the conductor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
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Evans Thomas
Fox Glen
Fenty Jesse A.
Hogan & Hartson L.L.P.
Lee Eddie
Ramtron International Corporation
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