Capacitively coupled DTMOS on SOI

Details Capacitively coupled DTMOS on SOI Capacitively coupled DTMOS on SOI

2000-06-28

2002-07-16

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S305000, C438S301000

Reexamination Certificate

active

06420767

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to the design of field effect transistors (FETS) and, more particularly, to a metal oxide silicon (MOS) transistor structure configured to operate as a dynamic threshold voltage metal oxide silicon (DTMOS) structure which facilitates mitigation of the operational voltage limitation associated with conventional DTMOS transistor structures.
BACKGROUND OF THE INVENTION
As is known in the art, transistors such as metal oxide silicon (MOS) transistors, have been formed in isolated regions of a semiconductor body such as an epitaxial layer which was itself formed on a semiconductor, typically bulk silicon, substrate. With an n-channel MOS field effect transistor (FET), the body is of p-type conductivity and the source and drain regions are formed in the p-type conductivity body as N
+
type conductivity regions. With a p-channel MOSFET, the body, or epitaxial layer, is of n-type conductivity and the source and drain regions are formed in the n-type conductivity body as P
+
type conductivity regions. It has been suggested that the semiconductor body, or layer, be formed on an insulating substrate, or over an insulation layer formed in a semiconductor substrate. Such technology sometimes is referred to as Silicon-on-Insulator (SOI) technology. Silicon-on-Insulator MOS technologies have a number of advantages over bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N
+
to P
+
spacing and hence higher packing density due to ease of isolation; and higher “soft error” upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Silicon-on-Insulator technology is characterized by the formation of a thin silicon layer for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources in drains are formed by, for example, implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor (e.g. metal) layer structure. Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). However, the floating body can introduce dynamic instabilities in the operation of such a transistor.
An SOI field effect transistor combines two separated immunity groups, generally formed by implantation, constituting the source and drain of the transistor with the general region (device body) between them covered by a thin gate insulator and a conductive gate. Typically no electrical connection is made to the channel region and therefore the body is electrically floating. Because the source and drain regions normally extend entirely through the thin silicon layer, the electrical potential of the body is governed by Kirchoffs current law, wherein the sum of the currents flowing into the body equals the sum of the currents flowing out of the body. Because the channel potential is dependent on the body voltage, the device threshold voltage varies as a function of the body voltage.
The boundaries between the channel region and the source and drain, respectively, form junctions which are normally reversed biased. Conduction in the channel region normally occurs immediately below the gate insulator in the region in which depletion can be controlled by a gate voltage. However, the junctions at the boundary of the source and drain also form a parasitic lateral bipolar transistor, which, in effect exists somewhat below the field effect transistor and may supplement desired channel current. On the other hand, the parasitic bipolar device cannot be controlled and under some bias conditions, the operation of the parasitic bipolar device may transiently dominate the operation of the field effect transistor and effectively occupy substantially the entire silicon layer at times when the channel current is not desired.
When the device is switching, the body is coupled to various terminals of the device because there are capacitances between the body and gate, body and source, and body and drain respectively. When the voltage at the various terminal changes, the body voltage changes as a function of time which in turn effects the device threshold voltage. In certain cases, this relationship may be harmful to a device (e.g., inverter). For example, when the gate of an inverter is switched on the drain is discharged (which is typically the output of the inverter)—thus the drain voltage falls when the gate is switched ON. Because the drain and body are capacitively coupled, when the drain voltage drops so does the body voltage. There is an inverse relationship between the body voltage and the threshold voltage. For an NMOS device, when the body voltage falls, the device threshold voltage increases. When the body voltage increases the threshold voltage decreases. Thus, the capacitive coupling between the drain and the body results in the device losing drive current as the device is being switched.
In SOI transistors there is a lack of a bulk silicon or body contact to the MOS transistor. In some devices, it is desirable to connect the p-type conductivity body in the case of an n-channel MOSFET, or the n-type conductivity body in the case of a p-channel MOSFET, to a fixed potential. This prevents various hysteresis effects associated with having the body potential “float” relative to ground. With bulk silicon MOSFETs such is relatively easy because the bottom of the bulk silicon can be easily electrically connected to a fixed potential.
SOI devices also exhibit a kink effect which originates from impact ionization. When an SOI MOSFET is operated at a relatively large drain-to-source voltage, channel electrons with sufficient energy cause impact ionization near the drain end of the channel. The generated holes build up in the body of the device, thereby raising the body potential. The increased body potential reduces the threshold voltage of the MOSFET. This increases the MOSFET current and causes the so-called “kink” in SOI MOSFET current vs. voltage (I-V) curves.
With regard to the lateral bipolar action, if the impact ionization results in a large number of holes, the body bias may be raised sufficiently so that the source region to body p-n junction is forward biased. The resulting emission of minority carriers into the body causes a parasitic npn bipolar transistor between source, body and drain to turn on, leading to loss of gate control over the MOSFET current.
A solution to controlling floating body effects and threshold voltages is known as a dynamic threshold metal oxide field effect transistor (DTMOS). A large improvement over regular MOSFET can be achieved when the gate and body of the MOSFET are electrically coupled. These devices offer improvements in power consumption in addition to reduced threshold voltages and faster switching times. This advantage is enhanced for SOI devices where base current and capacitances are appreciably reduced because of very small junction areas. However, these device are limited to operation of about a diode drop 0.6-0.8 volts. If the voltage rises above a diode drop, the body to source and body to drain parasitic diodes will turn on and gate control will be lost. This can result in a very high current from source to drain, which may even result in destruction of the device.
In view of the above, it is apparent that there is an unmet need in the art for a device which mitigates some of the negative effects mentioned above, relating to disadvantages of DTMOS SOI devices.
SUMMARY OF THE INVENTION
The present invention provides for a novel DTMOS device and method for making the same. The device of the present invention mit

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