Capacitive-summing switch-mode power conversion control

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

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323288, G05F 1565

Patent

active

060669438

ABSTRACT:
A controller for a power converter wherein there is provided a comparator having an output terminal and first and second input terminals. A switch-mode power train is coupled to the output terminal and operable to receive an unregulated input voltage and provide a regulated output voltage. A feedback network coupled to the switch-mode power train provides a voltage to the first input of the comparator. A ramp circuit includes a first capacitor divider having a first capacitor connected from a first input node to a first midpoint node and a second capacitor connected from the first midpoint node to a first reference voltage node and a second capacitor divider including a third capacitor connected from a second input node to a second midpoint node and a fourth capacitor connected from the second midpoint node to the first reference node. A first switch couples the first or second midpoint node to the second input of said comparator. A second switch couples a current source to the first input node when the first switch connects the first midpoint node to the comparator or to the second input node when the first switch connects the second midpoint node to the comparator. A third switch couples the first input node to the reference voltage node when the second switch couples the current source to the second input node. A fourth switch couples the second input node to the first reference voltage node when the second switch couples the current source to the first input node. A fifth switch couples the first midpoint node to the second reference voltage node when the second switch couples the current source to the second input node and a sixth switch couples the second midpoint node to the second reference voltage node when the second switch couples the current source to the first input node.

REFERENCES:
patent: 5436550 (1995-07-01), Arakawa
patent: 5600234 (1997-02-01), Hastings et al.
patent: 5689176 (1997-11-01), Deloy

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