Coded data generation or conversion – Digital code to digital code converters – To or from 'n' out of 'm' codes
Reexamination Certificate
1999-04-30
2001-02-27
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from 'n' out of 'm' codes
C326S108000
Reexamination Certificate
active
06195027
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to signal decode circuitry and a method of decoding input signals, and more particularly to circuitry and method for decoding input signals. In even more particular aspects the present invention relates to a signal decode technique in which capacitive charge is used to produce a reduced signal swing decode.
2. Background Information
Conventional prior art techniques for signal decoding have used bipolar DC bias current in a resistor network to provide cascode decoding. While this does provide a reduced voltage swing for decoding, this bipolar technique results in high power consumption. Thus it is desirable to provide a low or limited swing signal decoding that reduces power consumption.
SUMMARY OF THE INVENTION
According to the present invention, a method and structure for decoding n input signals and their complements to one of m output signals are provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.
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“Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's”, by Y. Nakagome, IEEE Journal of Solid State Circuits, vol. 28, No. 4 (Apr., 1993).
Bertin Claude L.
Fifield John A.
Houghton Russell J.
Miller Christopher P.
Tomashot Steven W.
Hogg William N.
International Business Machines - Corporation
Wamsley Patrick
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