Capacitive multidrop bus compensation

Details Capacitive multidrop bus compensation Capacitive multidrop bus compensation

2000-08-11

2004-06-01

Vo, Tim (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C327S109000

Reexamination Certificate

active

06745268

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to improving signal integrity of data signals applied to a bus and, more particularly, to the use of a compensating element for improving the signal integrity of a fully loaded high speed memory bus.
BACKGROUND OF THE INVENTION
Memory systems for computers provide many memory devices on a common bus to allow larger storage and transmission capacities than can be obtained with a single memory device. The memory devices are multiplexed on to a multidrop bus to reduce the pin count of a memory bus master or controller. Most of these systems requires user upgradeable or replaceable components to allow future expansion or repair of the memory subsystems. Typically, these systems are upgraded on a module basis, where the memory module (e.g., a dual in-line memory module or DIMM) has several devices on a small printed circuit board (PCB), and the module plugs into a connector that provides an electrical connection to the memory subsystem bus.
From a signal integrity standpoint, the provision of many memory devices on the bus can be problematic since these modules represent electrical stubs to the memory bus, which causes reflection on the bus. These reflections degrade the signal integrity an therefore, limit the maximum bandwidth or timing margin of the system. A robust electrical design is required in a high speed multidrop memory bus since the signal integrity must be acceptable to lightly loaded systems, that is, where only a small number of module slots are populated, heavily loaded systems, and for every device on the bus. A signal analysis of a typical memory subsystem has shown degraded signal integrity when the memory subsystem is fully loaded.
An example of a multidrop memory bus that must carefully balance the design for different loading characteristics is one which is intended for use with a double data rate synchronous dynamic random access memory (DDR SDRAM) main memory system. Such systems often have up to four memory slots that operate at a bus frequency of at least 133 MHz. Each memory slot can be populated with a single bank or double bank memory module. Balancing the design to be acceptable for both lightly and fully loaded situations can be challenging due to the number of slots, varying number of banks on the memory modules, and minor impedance mismatches between the memory modules and the memory bus.
Now referring to the drawings, where like reference numerals designate like elements, there is shown in
FIG. 1
a conventional memory system
1
. The memory system
1
includes a memory controller
200
, which may be coupled to a computer system via a local bus
1000
, which is also coupled to a processor
1100
and an expansion bus controller
1200
. The expansion bus controller
1200
is also coupled to one or more expansion buses
2000
, to which various peripheral devices such as mass storage devices, keyboard, mouse, graphics adapters, and multimedia adapters may be attached.
The memory controller
200
is also coupled to a memory bus
100
, which includes a plurality of sockets
106
a
-
106
d
. The sockets
106
a
-
106
d
may be left empty, or they can accept memory modules
300
a
-
300
d
. The memory modules may be double bank modules containing a first memory bank
301
a
-
301
d
and a second memory bank
302
a
-
302
d
, respectively, or the memory modules may be single banked modules containing only the first memory bank
301
a
-
301
d.
In order to operate the memory bus
100
at high speed, it is important to minimize signal reflections within the bus. To this end, the memory bus
100
includes a transmission line
101
that contains a source resistor
105
, which splits the transmission line
101
into a first segment
102
running from the memory controller to the source resistor
105
and a second segment
103
which runs from the source resistor
105
to a terminator
104
and which includes the plurality of sockets
106
a
-
106
d
. The terminator
104
includes a terminating resistor R
term
and a termination voltage source V
TT
. The use of the source resistor
105
, terminating resistor R
term
, and termination voltage source V
TT
is designed to match the memory bus
100
loaded impedance. When the memory bus is populated with memory modules
300
a
-
300
d
(via the sockets
106
a
-
106
d
), electrical stubs are created on the memory bus. These stubs reduce the effective impedance at that point on the bus, and this creates signal reflections which reduce the signal integrity and the maximum possible data rate that can be transferred on the bus.
When a four socket memory system has each socket populated by a double bank memory module, there are a large number of minor impedance mismatches leading to a significant decrease in signal integrity.
FIGS. 2A-2D
are examples of signal plots of read operations from each of the four double bank memory modules
300
a
-
300
d
, respectively. Similarly,
FIGS. 3A-3D
are examples of signal plots of write operations to each of the four double bank memory modules
300
a
-
300
d
, respectively.
Each signal plot shows a reference voltage
10
, an aperture box
20
for a first overdrive voltage, and an aperture box
30
for a second overdrive voltage. The reference voltage
10
is the baseline voltage of the memory bus
100
. Signals are detected on the memory bus
100
by either the memory controller
200
or the memory modules
300
a
-
300
d
when the voltage level of the signal differs by a minimum threshold, or overdrive voltage threshold, from the reference voltage
10
. For example, a logical low, sometimes called voltage output low or V
ol
, is detected on the memory bus
100
when the signal is at a voltage below the difference between the reference voltage
10
and the overdrive threshold voltage, while a logical high, sometimes called voltage output high or V
oh
, is detected when the signal is at a voltage above the sum of the reference voltage
10
and the overdrive voltage. Two separate overdrive voltage thresholds are shown on the signal plots because differing memory systems may require different overdrive thresholds. For example, the use of the larger second overdrive parameter may result in more accurate signal detection in a noisy environment. The two aperture boxes
10
,
20
illustrate the period of time when the plotted signals
40
differed by at least a first or second overdrive voltage threshold, respectively, to be detectable as either voltage output high or voltage output low. The plotted signals
40
are the signals that are seen by the memory controller
200
when the memory modules
300
a
-
300
d
drive signals onto the memory bus
100
(i.e., for the read operations illustrated in FIGS.
2
A-
2
D), as well as the signals see at each memory module
300
a
-
300
d
when the memory controller
200
drives signals onto the memory bus
100
(i.e., for the write operations illustrated in FIGS.
3
A-
3
D). In each case, the signals driven onto the memory bus
100
are a plurality of pseudo-random pulses.
As illustrated in
FIGS. 2A-2D
and
FIGS. 3A-3D
, the conventional system exhibits the following characteristics. When using the first overdrive threshold of 0.31 volts for read operations, the four memory modules have signal aperture times of 2.33 nanoseconds (ns), 2.29 ns, 2.33 ns, and 2.29 ns, respectively. For writes, the aperture times are 1.25 ns, 1.67 ns, 1.83 ns, and 1.92 ns, respectively. When using the second (larger) overdrive voltage threshold of 0.35 volts for read operations, the four memory modules have aperture times of 0.83 ns, 1.83 ns, 2.04 ns, and 2.00 ns, respectively. For writes, the aperture times are 0.71 ns, 1.25 ns, 1.54 ns, 1.58 ns. Thus, a fully loaded conventional memory bus
100
exhibits poor aperture times for write operations, especially when the overdrive threshold is set at 0.35 volts. Additionally, reads from the first memory module also exhibit poor aperture times at the 0.35 volt overdrive threshold.
Accordingly, there is a desire and need to improve the signal integrity of a fully loaded memory syst

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