Static information storage and retrieval – Systems using particular element – Resistive
Reexamination Certificate
2008-12-19
2011-11-15
Nguyen, Viet (Department: 2827)
Static information storage and retrieval
Systems using particular element
Resistive
C365S163000, C365S158000, C365S204000, C365S193000
Reexamination Certificate
active
08059447
ABSTRACT:
A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.
REFERENCES:
patent: 5623436 (1997-04-01), Sowards
patent: 5912839 (1999-06-01), Ovshinsky et al.
patent: 6141241 (2000-10-01), Ovshinsky et al.
patent: 6243290 (2001-06-01), Kurata
patent: 6292048 (2001-09-01), Li
patent: 6301161 (2001-10-01), Holzmann
patent: 6473332 (2002-10-01), Ignatiev et al.
patent: 6574145 (2003-06-01), Kleveland
patent: 6614688 (2003-09-01), Jeong
patent: 7068538 (2006-06-01), Devin
patent: 7068539 (2006-06-01), Guterman
patent: 7126841 (2006-10-01), Rinerson et al.
patent: 7301839 (2007-11-01), Li
patent: 7362604 (2008-04-01), Scheuerlein
patent: 7369428 (2008-05-01), Jeong
patent: 7391638 (2008-06-01), Fasoli
patent: 7420850 (2008-09-01), Fasoli
patent: 7447075 (2008-11-01), Guterman
patent: 7453730 (2008-11-01), Guterman
patent: 7869258 (2011-01-01), Scheuerlein et al.
patent: 2002/0057598 (2002-05-01), Sakamoto
patent: 2003/0117831 (2003-06-01), Hush
patent: 2006/0062043 (2006-03-01), Rohr
patent: 2006/0250836 (2006-11-01), Herner
patent: 2008/0025132 (2008-01-01), Fasoli
patent: 2009/0116280 (2009-05-01), Parkinson
patent: 2010/0085822 (2010-04-01), Yan et al.
patent: 2010/0265750 (2010-10-01), Yan et al.
patent: W02008/030351 (2008-03-01), None
Scheuerlein, et al., “Reverse Set With Current Limit for Non-Volatile Storage,” U.S. Appl. No. 12/339,313, filed Dec. 19, 2008.
Fasoli, et al., “Smart Detection Circuit for Writiting to Non-Volatile Storage,” U.S. Appl. No. 12/339,327, filed Dec. 19, 2008.
Scheuerlein, “Pulse Reset for Non-Volatile Storage,” U.S. Appl. No. 12/339,363, filed Dec. 19, 2008.
PCT International Search Report dated Oct. 22, 2009, PCT Patent Application No. PCT/US2009/048955.
Written Opinion of the International Searching Authority dated Oct. 22, 2009, PCT Patent Application No. PCT/US2009/048955.
Response to Written Opinion, dated Mar. 11, 2011, European Patent Application No. 09771207.9.
Fasoli Luca G.
Scheuerlein Roy E.
Yan Tianhong
Nguyen Viet
SanDisk 3D LLC
Vierra Magen Marcus & DeNiro LLP
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