Capacitive data and clock transmission between isolated ICs

Details Capacitive data and clock transmission between isolated ICs Capacitive data and clock transmission between isolated ICs

2000-08-11

2004-04-27

Chin, Stephen (Department: 2634)

Pulse or digital communications

Cable systems and components

C375S288000

Reexamination Certificate

active

06728320

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to isolation systems, and more particularly relates to methods and apparatus for transmission of data and clock signals between integrated circuits isolated from one another through capacitors.
BACKGROUND OF THE INVENTION
Electrical isolation is a requirement in many applications. For example, the telephone line which runs from the local exchange to the customer premises is prone to high voltage surges due to lightening, high voltage lines in proximity to the telephone lines, etc. Frequently, sensitive circuitry in customer premises equipment, such as the computer modem, is coupled to telephone lines, and such circuitry must be protected from such surges. The high voltage surges appearing on telephone lines usually appear on the TIP and RING lines as common mode signals. The modem should be designed to isolate about 1.5 kV of common mode signals on the telephone line from the circuitry.
Traditionally, transformers have provided such isolation. However, transformers are expensive and bulky. As a result, recently, capacitive isolation has been employed, in an effort to reduce the size and cost of the isolation system. In such systems high frequency digital signals are sent across the capacitors, rather than analog signals. This allows the capacitors to have a low capacitance. This keeps the size of the capacitors small at the voltage ratings desired for this purpose, i.e., in the range of 1.5 kV. This creates the need to draw power from the telephone line.
An example of an approach to this type of isolation is found in U.S. Pat. No. 5,870,046, which is entitled “Analog Isolation System With Digital Communication Across a Capacitive Barrier,” and is assigned to Silicon Laboratories Inc. However, this approach has extensive circuitry, requiring considerable chip area, and is therefore costly. For example, it calls for the use of a phase locked loop (“PLL”) for clock recovery. A phase locked loop takes considerable static current during operation. Hence, its power consumption is high, which is undesirable. Further, PLLs take a large amount of silicon area, which is also undesirable. Still further, when the line side of the interface is sending data, the PLL is free running. However, the PLL should sustain the correct frequency for a considerable amount of time, in order to minimize lock time when the direction of data is reversed, putting a considerable demand on the accuracy of the nominal frequency of the PLL oscillator, and its stability, again adding to cost.
Thus, there is a need for a low cost system for providing electrical isolation between integrated circuits having data and clock signals transmitted between them. Further, there is a need for such a system in which the electrical isolation is provided by capacitors.
SUMMARY OF THE INVENTION
According to one aspect of the present invention a method is provided for transfer of digital data, comprising a succession of one values and zero values, across a capacitive interface. The interface includes a first capacitor and a second capacitor linking a first circuit to a second circuit. The first capacitor and the second capacitor each has a first port connected to the first circuit and a second port connected to the second circuit. First digital data is transferred from the first circuit to the second circuit, and a reference clock is provided by the first circuit and transmitted with the first data to the second circuit for recovery thereby. The method includes the following steps. A first set of bi-level signals representing the zero values of the first data is applied to the first port of the first capacitor, such that a repeating level transition of the reference clock corresponds to a first level transition of the first set of bi-level signals. A second set of bi-level signals representing the one values of the first data is applied to the first port of the second capacitor, such that the repeating transition of the reference clock corresponds to a second level transition of the second set of bi-level signals. The clock and data are then recovered.
According to another aspect of the present invention there is provided a method for transfer of digital data across a capacitor linking a first circuit to a second circuit. The capacitor has a first port connected to an output of a first tri-state buffer of the first circuit, and the capacitor has a second port connected to an output of a first tri-state buffer of the second circuit. A reference clock having a repeating transition from a first level to a second level is provided by the first tri-state buffer to the second circuit through the capacitor, and a succession of digital data signals are transferred by the second tri-state buffer to the first circuit through the capacitor. The method includes the following steps. The first tri-state buffer provides a first one of the repeating transitions to the capacitor, at a first clock time. The first tri-state buffer enters tri-state, after a first predetermined delay period following the first clock time. The second tri-state buffer provides one of the digital data signals to the capacitor, after a second predetermined delay period, longer in duration than the first predetermined delay period, following the first clock time, at a second clock time. The second tri-state buffer enters tri-state prior to a third clock time. Then, if the capacitor is not at the first level, the ports of the capacitor are changed to the first level. The foregoing steps are repeated to transfer additional digital data signals.
According to yet another aspect of the present invention there is provided a method for bi-directional transfer of digital data, comprising a succession of one values and zero values, across a capacitive interface. The interface has a first capacitor and a second capacitor linking a first circuit to a second circuit. The first capacitor and the second capacitor each has a first port connected to the first circuit and a second port connected to the second circuit. First digital data is transferred from the first circuit to the second circuit, and second digital data is transferred from the second circuit to the first circuit. In addition, a reference clock having cycles, the cycles having a first portion and a second portion, is provided to the first circuit and transmitted with the first data to the second circuit for recovery thereby. The method includes the following steps. A first set of bi-level signals representing, during the first portion of the reference clock cycles, the zero values of the first data is applied to the first port of the first capacitor, such that a repeating transition of the reference clock corresponds to a first level transition of the first set of bi-level signals. A second set of bi-level signals representing, during the first portion of the reference clock cycles, the one values of the first data is applied to the first port of the second capacitor, such that the repeating transition of the reference clock corresponds to a second level transition of the second set of bi-level signals. The first digital data is recovered in the second circuit, and the clock is recovered in the second circuit to provide a recovered clock to the second circuit. A third set of bi-level signals representing the zero values of the second data is applied to the second port of the first capacitor during the second portion of the reference clock cycles, and a fourth set of bi-level signals representing the one values of the second data is applied to the second port of the second capacitor during the second portion of the reference clock cycles.


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patent: 6587560 (2003-07-01), Scott et al.

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