Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-01-19
2001-07-10
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S185180
Reexamination Certificate
active
06259635
ABSTRACT:
TECHNICAL FIELD
The present invention refers to the field of semiconductor memories, particularly of non-volatile type memories. More specifically, the invention concerns a circuit for the regulation of the word line voltage during the step of reading of a non-volatile memory, particularly but not exclusively a multilevel non-volatile memory (that is a memory whose cells are programmable to one of more levels of threshold voltage, and that are therefore capable to store more than one bit per single cell), for instance a multilevel non-volatile memory integrated in a device with a single supply voltage.
BACKGROUND OF THE INVENTION
As known, for the reading of multilevel non-volatile memories it is necessary to provide the addressed word line of the matrix of memory cells with a stable and accurate voltage, with the aim of guaranteeing optimal conditions for the reading operation. In multilevel memories the difference between the values of memory cell threshold voltage corresponding to the different logical states that are memorizable in the same cell is reduced with respect to the case of traditional cells of a non-volatile memory with two programming levels that can memorize one bit only.
It results that the reading voltage for the word lines addressed in turn must be supplied through a voltage regulator, as shown in
FIG. 1
, where there is a voltage regulator
1
supplied with a voltage V
sup
that is generally different from the memory supply voltage V
DD
. A row decoding circuit
2
decodes word line addresses Ai whose logic levels “0” and “1” correspond to the ground voltage and to the memory supply voltage V
DD
. A voltage elevator (high switch) circuit
3
increases the value of voltage corresponding to the logical state “1” from V
DD
to a higher value V
R
. A final driving stage
4
for a respective word line (word line driver) is supplied with the voltage V
reg
provided by the regulator
1
. C
R
represents the global capacitive load connected with the output of the regulator
1
when no word line is selected.
In multilevel memories the voltage V
sup
is typically higher than the memory supply voltage V
DD
, which in the devices of the current generation has a nominal value of 3 V. The more commonly adopted technique for the generation of voltages higher than V
DD
inside a MOS technology integrated circuit is the utilization of voltage multiplication circuits with a charge pump. Circuits of this type are capable of providing the required values of voltage, but they generally have limited ability to deliver output current; and when they are started (for instance when the integrated circuit is turned on or when returning from a condition of disabling (“power down”) or of quiescence (“stand-by”), in which the circuit is turned off with the purpose of obtaining a saving in power consumption) they require of a certain time in order to bring the output voltage from the initial zero value to the desired value, and this time is greater the higher the capacitance value of the same circuit output charge.
The elevator circuit
3
can be for instance made up of a pull-up P-channel MOS transistor connected between the inlet of the word line driver
4
and the supply line V
reg
of the same driver
4
and with the gate electrode grounded. Other known techniques can be used for this purpose.
The enabling of a specific word line of memory cells takes place when the address of the location of memory to be read changes, in the example herein shown the word line address signals Ai, or in any case when an opportune signal is provided that indicates that one (or more) determined word line must be selected and activated. The decoder
2
generates output logic signals that are suitable to select the desired word line through the final stages
4
. Each final stage
4
is essentially made up of a CMOS inverter.
FIG. 2
schematically illustrates a circuit that can typically be utilized for the voltage regulator
1
of FIG.
1
. The voltage regulator is substantially made up of a loop comprising an operational amplifier A connected in negative feedback through two resistors R
1
, R
2
, which provides an output voltage V
reg
with nominal value equal to V
R
. The operational amplifier A receives a fixed reference voltage V
BG
on the non-inverting terminal. If the gain of the operational amplifier is sufficiently high, ignoring non-idealities as the offset voltages, the output voltage of the regulator
1
is equal to:
V
reg
=V
BG
×(1+
R
1
/
R
2
)
In an integrated circuit the ratio between the resistances of the two resistors R
1
and R
2
can be realized with a very high degree of precision, still neglecting non-ideal effects, so that the accuracy of the value of the generated voltage V
reg
substantially depends on the accuracy of the value of the reference voltage V
BG
. The latter can be obtained in a known way by means of a generator of “band-gap” reference voltage that generates a very accurate voltage and that is provided with good stability even with variable parameters such as supply voltage and temperature.
The single word line is perceived by the regulator
1
as a capacitive load C
W
(more precisely, the word line is a distributed RC load), since the word line does not determine an absorption of direct current, but it has non-negligible stray capacitance, substantially connected between said word line and ground, or between the word line and other nodes (for descriptive simplicity the global stray capacitance C
W
can however be considered to be connected between the word line and the ground).
When a determined word line of the memory matrix (array) is not being addressed, it is grounded, and therefore the capacitance C
W
associated with it is discharged.
When the word line is addressed, its voltage must be brought by the respective driver
4
to the value required for the correct execution of the reading operation, a value that will be indicated by V
R
. More precisely, for a correct execution of the reading operation the voltage of the word line must be comprised within a determined interval around the value V
R
. When the word line is selected, it is connected with the output of the voltage regulator
1
by the driver
4
. The voltage V
reg
supplied by the regulator, that in static conditions is ideally equal to V
R
, undergoes a decrement. The decrement is due to a phenomenon of “charge sharing” between the total load capacitance C
R
connected with the output of the regulator when no word line is selected, and the capacitance C
W
of the word line. Whenever for reasons of memory architecture more word lines are selected simultaneously, then the load that is connected to the output of the voltage regulator (and that will give rise to the phenomenon of charge sharing) will consist of the total capacitive load of all the word lines that have simultaneously been selected. Hereinafter, the symbol C
W
will refer to the total load that is connected with the output of the regulator.
The decrement in the output voltage of the voltage regulator is very quick, as the phenomenon of charge sharing is very fast, and it can be excessive in the sense that the value of the voltage V
reg
goes out of the interval required for the correct execution of the reading operation. The recovery of the voltage V
reg
, that is the recovery of the output voltage of the regulator within the interval that allows execution of an optimal reading, must be sufficiently fast, so that the time of access of the memory is not degraded and, above all, no erroneous reading occur.
Purely as an example, considering the case of EEPROM Flash memories in sub-micrometric technology that are organized in memory sectors with appropriate size, the values involved are reasonably the following:
V
R
=6 V;
C
R
=100 pF;
C
W
=3 pF;
&Dgr;V
max
=50 mV,
where &Dgr;V
max
indicates the maximum error allowed for the voltage V
reg
during the reading step; in other words, the recovery of the voltage V
reg
after the selection of the new word line (or word lines) is considered to be obtain
Khouri Osama
Micheloni Rino
Motta Ilaria
Sacco Andrea
Torelli Guido
Galanthay Theodore E.
Phan Trong
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
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