Capacitance sensing method of reading a ferroelectric RAM

Details Capacitance sensing method of reading a ferroelectric RAM Capacitance sensing method of reading a ferroelectric RAM

2003-04-11

2004-10-12

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06804140

ABSTRACT:

This application claims the benefit of Taiwan application Ser. No. 91107883, filed Apr. 17, 2002.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of reading a ferroelectric RAM (FeRAM), and more particularly to a method of reading a FeRAM by capacitance sensing.
2. Description of the Related Art
The ferroelectric random access memory (FeRAM) uses ferroelectric capacitors as storage media. The ferroelectric capacitor can be polarized in either positive polarized state or negative polarized state, which represents the data stored therein.
FIG. 1
is the transition diagram of the polarized state of the ferroelectric capacitor. The transition curve of the polarized state is hysteretic, which means that a positive voltage is required to convert the negative state into the positive state, and a negative voltage is required to convert the positive state into the negative state. The FeRAM has the potential to replace the current flash memory because no power is needed for the ferroelectric capacitor to maintain its polarized state. The FeRAM also has the potential to replace the current dynamic random access memory (DRAM) because only low voltage is required for changing of the polarized state of the ferroelectric capacitor.
The variable capacitance of the ferroelectric capacitor is another characteristic thereof. It is well known that the capacitance C=&Dgr;Q/&Dgr;V, wherein Q is the electric charge, and V is the voltage of the capacitor. The capacitance C is in proportion to the slope of the transition curve because the polarized state P is in proportion to the change in electric charge Q. Therefore, the capacitance C becomes larger if the slope of the transition curve becomes steeper. Accordingly, the capacitance in the transition state is larger than that in the stable state.
FIG. 2A
is a diagram of a memory cell of a FeRAM. The memory cell is of a 1T1C type, which means the memory cell includes a transistor T and a ferroelectric capacitor Cf. The capacitor Cf is coupled between the bit line BL and the plate line PL. The voltage of the capacitor Cf is the voltage difference between the plate line PL and the bit line BL when the word line (WL) is enabled.
FIG. 2B
is a diagram of a memory cell of another FeRAM. The memory cell is of a 2T2C type, which means the memory cell includes 2 transistors, T and T′, and two ferroelectric capacitors, Cf and Cf′. The memory cell also includes a sense amplifier SA for amplifying the voltage difference between the bit line BL and BL′so as to read the data stored in the memory cell. In addition, the bit line with higher voltage is pulled to the high level and the bit line with lower voltage is pulled to the low level by the sense amplifier SA. The sense amplifier SA is enabled according to a sensing enable signal SAE.
Two reading methods of the FeRAM are used in general: the plate-line driving method and the bit-line driving method.
FIG. 3
is a timing diagram of reading the FeRAM in
FIG. 2B
by the plate-line driving method. Initially, the word line WL in period T1 is enabled to turn on the transistors T and T′. Then, the plate line PL is enabled and pulled high. The polarized state P and P′ of the capacitor Cf and Cf′, respectively, are positive as shown in
FIG. 3
according to the positive voltages of the capacitors Cf and Cf′. The capacitance of the capacitor Cf′ is larger than that of the capacitor Cf because the polarized state of the ferroelectric capacitor Cf′ is in transition phase from the negative state to the positive state. Then, the sense amplifier SA in period T3 is enabled to amplify the voltage difference between the bit line BL and BL′ for reading the stored data. At this time, the bit line BL′ is pulled high because the voltage thereof is higher than that of the bit line BL, and thus the bit line BL is pulled low. The voltage of the capacitor Cf′ is almost zero because the voltages of the bit line BL′ and the plate line PL are high, and thus the polarized state P is positive, as shown in FIG.
3
. The periods T1 and T2 are of the driving procedure for differentiating the voltage difference between the bit lines BL and BL′. The period T3 is of the sensing procedure.
The polarized state P′ of the capacitor Cf′ is positive in period T3, but the initial polarized state P′ is negative at period T1. Thus, a recovery procedure is performed for the recovery of the polarized state P′. First, plate line PL in period T4 is disabled. The polarized state P′ becomes negative because the voltage of the capacitor Cf′ becomes negative. Then, the voltage of the capacitor Cf′ becomes zero because the voltage of the bit line BL falls, and the recovery procedure is completed.
The plate-line driven method generates the voltage difference between the bit lines BL and BL′ according to the polarized states of the capacitors Cf and Cf′ by first enabling the plate line PL and the word line WL. The bit-line driven method generates the voltage difference between the bit lines BL and BL′ according to the polarized states of the capacitors Cf and Cf′ by first enabling the bit lines BL and BL′, which is well known and not described here.
However, the reading speed of the prescribed plate-line driven method and the bit-line driven method are not quick enough because both of the methods each require three procedures: driving, sensing, and recovery, which needs 5 periods in total.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved and simplified method of reading a FeRAM more quickly.
The invention achieves the above-identified object by providing a capacitance sensing method of reading a FeRAM (Ferroelectric Random Access Memory). The FeRAM includes a word line, a bit line, an inverse bit line, a first switch, a second switch, a first ferroelectric capacitor, a second ferroelectric capacitor, a plate line, and a latch sense amplifier. The bit line, the first switch, the first ferroelectric capacitor, and the plate line are connected serially. The inverse bit line, the second switch, the second ferroelectric capacitor, and the plate line are connected serially. The word line switches the first and the second switches. The latch sense amplifier is coupled to the bit line and the inverse bit line. The method includes the following steps. First, turning on the first and the second switches by enabling the word line. Then, changing the voltages of the bit line and the inverse bit line by enabling the latch sense amplifier according to the first and the second ferroelectric capacitors. Then, the data stored in the FeRAM is outputted according to the voltage difference between the bit line and the inverse bit line.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.


REFERENCES:
patent: 5572459 (1996-11-01), Wilson et al.
patent: 6229730 (2001-05-01), Kato
patent: 6731530 (2004-05-01), Miwa et al.
patent: 6731554 (2004-05-01), Jacob et al.
patent: 480483 (2003-03-01), None

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