Capacitance modeling

Details Capacitance modeling Capacitance modeling

2008-06-11

2011-11-08

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Testing or evaluating

C716S106000, C716S111000, C703S002000, C703S004000

Reexamination Certificate

active

08056043

ABSTRACT:
A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (∈1) and the substrate is a second dielectric with a second permittivity (∈2). The method models the capacitance (C1) for values of the first and second permittivity (∈1, ∈2) based on known capacitance (C2) computed for a basis structure with the same first permittivity (∈1) and a different second permittivity (∈2). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C1) through one or more known capacitances (C2).

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Office Action dated Feb. 18, 2001 in a related U.S. Patent Application, namely U.S. Appl. No. 12/137,257.
Notice of Allowance dated Jun. 10, 2011 in a related U.S. Patent Application, namely U.S. Appl. No. 12/137,257.

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