Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-04
2011-01-04
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07865851
ABSTRACT:
The present invention improves the accuracy of parasitic capacitance extraction of IC designs with floating fill. One embodiment of the present invention approximates the coupling capacitances of fill nets beyond an exact-approximation level by a fill net elimination method whereby actual capacitances of the fill net to the variable level are fully extracted and remaining capacitances are approximated.
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Mentor Graphics Corporation
Rossoshek Helen
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