Semiconductor device manufacturing: process – Electron emitter manufacture
Reexamination Certificate
1999-06-07
2001-04-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Electron emitter manufacture
C438S020000
Reexamination Certificate
active
06218204
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabrication, and more particularly to accurately measuring topology of a wafer, thereby allowing reduction of focusing error of an exposure process.
2. Description of Related Art
In a DRAM of interest, a lower electrode layer in the information storing capacitor of each memory cell extends vertically upwards, the difference in height between a memory cell array region( or area) and a peripheral circuit region( or area) is very large.
Scanner systems require accurately controlled-focusing and tilting so as to obtain exposure reliability to a wafer whereon a variety of structures are formed. One example of a system which controls the focusing and tilting is a capacitance gauge tracking system(hereinafter referred to “CGTS”)(see FIG.
1
). The CGTS tracks the capacitance between a wafer surface and a capacitance gauge to control focusing and tilting before the exposure process. Another example of system is known optical multi-point focusing system.
FIG. 1
schematically shows a CGTS
16
. As illustrated, a wafer
12
is mounted over a wafer stage
10
. The CGTS
16
measures the capacitance between the wafer
12
surface and a capacitance gauge
14
by moving the grounded wafer
12
or the capacitance gauge
14
according to X-Y direction. The resulting equivalent circuits in accordance with tracking of
FIG. 1
are schematically illustrated in
FIGS. 2A and 2B
, respectively at peripheral region and cell array region. In
FIGS. 2A and 2B
, a reference numeral “R” represents equivalent resistance of the wafer, “C-oxide” represents capacitance of an oxide layer at the peripheral region, “R
p
” represents equivalent resistance of a polysilicon, “C-air” represents capacitance of an air between the wafer
12
and capacitance gauge
14
, and a reference numeral “
20
” represents constant current source applied from CGTS
16
.
From the equivalent circuits of
FIGS. 2A and 2B
, C-peri(capacitance of peripheral region), C-array(capacitance of cell array region), C(capacitance) are given by the following equations,
C-array=C-air (2)
C=&egr;(A/d) (3)
where “&egr;” is permittivity, “A” is an area, and “d” is a distance between adjacent conductors.
Permittivity of air is about 1 and permittivity of an oxide layer is about 4. From the above mentioned equations, C-air(capacitance of air) becomes A/100, and C-oxide(capacitance of oxide) becomes 4A. If the peripheral region is filled with about 1 micrometers thick oxide layer, C-peri becomes A/104 from equation 1. There should be the difference of about 4 micrometers in height between cell array region and peripheral region if the same C-peri(i.e., A/104) is obtained by using air instead of the oxide.
However, the real height difference there between is about 0.3 micrometers. Therefore, CGTS incorrectly tracks the capacitance of the wafer surface(i.e., calculated capacitance differs from the real capacitance), since capacitances of the polysilicon(cell array region) and the oxide layer(peripheral region) are different from one another. As a result, defocusing problems can arise during the exposure process.
SUMMARY OF THE INVENTION
The present invention is therefore directed to a method of measuring a topology of a wafer and a wafer to be measured which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
The above and other objects may be realized by forming a conductive layer over a wafer to compensate for variation of capacitance caused by high stacked capacitor in the cell array region. Due to the conductive layer over the wafer surface, real topology of the wafer can be accurately measured by the capacitance gauge tracking system without error due to material and structure below the conductive layer.
The above and other objects may also be met be provided such a wafer to be measured including a conductive layer over a selected region and in a contact with the selected region.
The conductive layer may be made of one selected from the group consisting of titanium nitride layer, metal layer and conductive photoresist layer. The conductive layer may also serve as an anti-reflection coating(ARC) layer.
These and other objects of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating the preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 4103226 (1978-07-01), Fromson et al.
patent: 5744856 (1998-04-01), Rostoker
Hong Jin-Seog
Kang Ho-young
Lee Jung-Hyeon
Jones Volentine, L.L.C.
Nelms David
Nhu David
Samsung Electronics Co,. Ltd.
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