Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent
1995-08-04
1996-12-10
Westin, Edward P.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
326101, 326 93, 327292, 327297, H03K 1716, H03K 1900
Patent
active
055834493
ABSTRACT:
A system in which line reflections in a clock distribution network are cancelled by providing the clock distribution network with a branching point and suitably arranging recipient devices with respect to the branching point to provide for clock pulse reflection cancellation and attenuation. Moreover, the system can be arranged so that clock pulse reflections are not received as pulses which are discrete from legitimate clock pulses. The system also provides capability for reducing electromagnetic interference.
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patent: 5122693 (1992-06-01), Honda et al.
patent: 5270592 (1993-12-01), Takahashi et al.
patent: 5414832 (1995-05-01), Denneau et al.
patent: 5416861 (1995-05-01), Koh et al.
Buuck David C.
Dhuey Michael J.
Apple Computer Inc.
Roseen Richard
Westin Edward P.
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