Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-05-20
2008-05-20
Louis-Jacques, Jacques H (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S200000, C365S189050
Reexamination Certificate
active
10635348
ABSTRACT:
Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes. Accordingly, the CAM can be debugged to isolate memory failures from priority encoder failures, which significantly reduces the need for design changes. The present invention provides the ability to test the CAM functions very efficiently, thereby reducing the test time.
REFERENCES:
patent: 4680760 (1987-07-01), Giles et al.
patent: 5289403 (1994-02-01), Yetter
patent: 5491703 (1996-02-01), Barnaby et al.
patent: 6539466 (2003-03-01), Riedlinger
patent: 6550034 (2003-04-01), Riedlinger et al.
patent: 6564344 (2003-05-01), Bui et al.
patent: 6691252 (2004-02-01), Hughes et al.
patent: 6999331 (2006-02-01), Huang
Harris George Ernest
Sheffield Bryan
Ward Dwayne
Brady W. James
Louis-Jacques Jacques H
Radosevich Steven D
Stewart Alan K.
Telecky , Jr. Frederick J.
LandOfFree
CAM test structures and methods therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with CAM test structures and methods therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CAM test structures and methods therefor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3957470