Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-08-23
2004-03-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S049130, C365S149000
Reexamination Certificate
active
06700827
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit memory devices, and in particular to content addressable memory (CAM) circuits.
DISCUSSION OF RELATED ART
Conventional random access memory (RAM) arrays include RAM cells (e.g., static RAM (SRAM) cells, dynamic RAM (DRAM) cells, and non-volatile RAM (NVRAM) cells) that are arranged in rows and columns, and addressing circuitry that accesses a selected row of RAM cells using address data corresponding to the physical address of the RAM cells within the RAM array. A data word is typically written into a RAM array by applying physical address signals to the RAM array input terminals to access a particular group of RAM cells, and applying data word signals to the RAM array input terminals that are written into the accessed group of RAM cells. During a subsequent read operation, the physical address of the group of RAM cells is applied to the RAM array input terminals, causing the RAM array to output the data word stored therein. Groups of data words are typically written to or read from the RAM array one word at a time. Because a relatively small portion of the entire RAM array circuitry is activated at one time to perform each data word read/write operation, a relatively small amount of switching noise within the RAM array, and the amount of power required to operate a RAM array is relatively small.
In contrast to RAM arrays, content addressable memory (CAM) arrays include memory cells (e.g., SRAM cells, DRAM cells, or NVRAM cells) in response to their content, rather than by a physical address. Specifically, a CAM array receives a data value that can be compared with all of the data words stored in the CAM array. In response to each unique data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value. Because large amounts of data can be searched at one time, CAM arrays are often much faster than RAM arrays in certain systems, such as search engines.
While CAM arrays are faster than RAM arrays in performing search functions, they consume significantly more power and generate significantly more switching noise than RAM arrays. In particular, in contrast to RAM arrays in which only a small portion of the total circuitry is accessed during each read and write operation, significantly more power is needed (and noise is generated) in a CAM array because a relatively large amount of circuitry is accessed during each lookup operation.
To reduce the total power consumed by CAM arrays, there is a trend toward producing CAM arrays that operate on low system voltages. To facilitate lower voltages, the integrated circuit (IC) fabrication technologies selected to produce such CAM arrays utilize smaller and smaller feature sizes. In general, the smaller the feature size of an IC, the lower the system voltage that is used to operate the IC. However, when IC feature sizes and system voltages are reduced too much, the amount of charge stored at each node within the CAM array becomes so small that a soft error problem arises, which is discussed below with reference to FIG.
12
.
FIG. 12
is a simplified cross sectional view showing an N-type diffusion (node)
50
formed in P-type well (P-WELL)
51
, which is exemplary of a typical IC feature (e.g., a drain junction utilized to form an N-type transistor). Dashed line capacitor
52
represents the capacitance of node
50
, and indicates that node
50
stores a positive charge.
As indicated in
FIG. 12
, if an energetic particle, such as an alpha-particle (&agr;), from the environment or surrounding structure strikes the N-type diffusion of node
50
, then electrons (e) and holes (h) will be generated within the underlying body of semiconductor material (i.e., in P-well
51
). These free electrons and holes travel to the node
50
and P-well
51
, respectively, thereby creating a short circuit current that reduces the charge stored at node
50
. If the energy of the alpha-particle is sufficiently strong, or if the capacitance
52
is too small, then node
50
can be effectively discharged. When node
50
forms a drain in an SRAM cell and the charge perturbation is sufficiently large, the stored logic state of the SRAM cell may be reversed (e.g., the SRAM cell can be flipped from storing a logic “1” to a logic “0”). This is commonly referred to as a “soft error” because the error is not due to a hardware defect and the cell will operate normally thereafter (although it may contain erroneous data until rewritten).
Soft errors also arise due to other mechanisms, such as switching noise. As discussed above, switching noise is significantly higher in CAM arrays than in conventional RAM arrays, thereby making the problem of soft errors even greater in CAM arrays.
Erroneous data or loss of data integrity due to soft errors are major causes of system failure (“crash”). It is widely accepted that system failures and down time in electronic systems claim a heavy toll in terms of cost and performance of such systems. When a system crashes, unrecoverable data may be lost. Even in the best case, a user suffers a great deal of inconvenience. Hence, system designers are constantly trying to minimize the occurrence of soft errors in their systems in order to prevent costly system failures.
Many approaches have been proposed for dealing with soft errors, such as increased cell capacitance or operating voltage, and the use of error detection schemes (such as using parity bits or error checking and correcting (EDC) codes). While these proposed approaches are suitable for standard RAM arrays, they are less desirable in CAM arrays. As pointed out above, CAM arrays inherently consume more power than RAM arrays. Therefore, while increased cell size and/or operating voltage can be tolerated in a RAM array, such solutions are less desirable in a CAM arrays. Moreover, adding error detection schemes to CAM arrays increase the size (and, hence, the cost) of the CAM arrays, and further increase power consumption.
Accordingly, what is needed is a memory system that addresses the soft error problem associated with a CAM array of the system without greatly increasing the cost and power consumption of the CAM array.
SUMMARY
The present invention is directed to a CAM circuit including a CAM array, one or more RAM arrays, and control and interface circuits that coordinate the operation of the CAM array and RAM array(s) such that data stored in the CAM array is systematically refreshed using data stored in the RAM array(s). In addition, the CAM circuit includes an error detection or an error detection and correction (EDC; also known as error checking and correction, or ECC) circuit connected to the interface circuit for selectively performing error detection or EDC functions (e.g., detecting and, if necessary, correcting the data stored in the RAM array(s)) before writing the data to the CAM array. By providing separate RAM array(s) for refreshing the data values stored in the CAM array, and by performing the error detection or EDC functions on data words read from the RAM array(s) prior to being written to the CAM array, highly reliable CAM operations are provided without greatly increasing the cost and power consumption of the CAM array.
In one embodiment of the present invention, each data word written to the RAM array(s) includes an associated set of check bits, which are generated according to the Hammings single-bit code scheme, that can be utilized to detect and correct single bit errors in the data word, and detect (but not correct) some multiple bit errors in the data word. The check bits can be transmitted with the data bits when originally written to the CAM circuit. Alternatively, when only the data bits are written to the CAM circuit, the check bits may be generated by the EDC circuit when the data bits are first written to the RAM array(s), or generated when the data bits are first read from the RAM array(s). Duri
Lien Chuen-Der
Miller Michael J.
Bever Hoffman & Harms, LLP.
Hoang Huan
Integrated Device Technology Inc.
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