CAM array with minimum cell size

Details CAM array with minimum cell size CAM array with minimum cell size

2000-10-02

2001-07-24

Nelms, David (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070

Reexamination Certificate

active

06266263

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to content addressable memory (CAM) arrays. More specifically, the present invention relates to ternary and higher order CAM cells and methods for operating these cells in a CAM array.
DISCUSSION OF RELATED ART
Unlike conventional random access memory (RAM) arrays, CAM arrays include memory cells that are addressed in response to their content, rather than by a physical address within a RAM array. That is, data words stored in a RAM array are accessed by applying address signals to the RAM array input terminals. In response to each unique set of address signals, a RAM array outputs a data value that is read from a portion of the RAM array designated by the address. In contrast, a CAM array receives a data value that is compared with all of the data values stored in rows of the CAM array. In response to each unique data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value.
CAM arrays are useful in many applications, such as search engines. For example, assume an employee list is searched to identify all employees with the first name “John”. The first names are written into a CAM array such that they are stored in a predetermined order (e.g., according to employee number). The compare data value (“John”) is then applied to the CAM input terminals. When one or more stored data values match the compare data value (a match condition), the match line coupled to the one or more matching rows of CAM cells generates a match value (e.g., a logic highvalue) output signal. The rows having CAM cells having stored data values that do not match the compare data value (a no-match condition) generate a no-match value (e.g., a logic low value) output signal on the associated match lines. By identifying which rows have associated high match lines, and comparing those row numbers with the employee number list, all employees named “John” are identified. Note that some CAM arrays generate a logic low value as a match value output signal. In contrast, to search a RAM array containing the same employee list, a series of addresses must be applied to the RAM array so that each stored data value is read out and compared with the “John” data value. Because each RAM read operation takes one clock cycle, a relatively large amount of time is required to read and compare a particular data value with all data values stored in a RAM array.
CAM cells are typically defined by the number of data values that they store. For example, binary CAM cells stores one of two logic values: a logic high value or a logic low value. Ternary CAM cells store one of three logic values: a logic high value, a logic low value, and a “don't care” logic value. A “don't care” logic value is a logic value that produces a match condition for any applied compare data value. Higher order CAM cells store additional data values. For example, a CAM cell storing four states will have one of a logic high value, a logic low value, a logic high “don't care” value, and a logic low “don't care” value. Thus, a CAM cell storing four states beneficially stores a data value (e.g., a high or low value) and simultaneously indicates whether that data value is to be involved in a match operation (e.g., a logic high or a logic high “don't care”). As a result, a read operation on a four-state CAM cell storing a “don't care” value distinguishes the “don't care” value read from the CAM cell as either a logic high “don't care” value or a logic low “don't care” value.
When the logic value stored in a ternary CAM cell matches an applied data value, assuming all other CAM cells coupled to the CAM array row also match, then the voltage on the match line coupled to the ternary CAM cell is maintained at the match value (e.g., a logic high value), thereby indicating that a match has occurred. In contrast, when the logic value stored in the ternary CAM cell does not match an applied data value, then the voltage on the match line coupled to the ternary CAM cell is changed to the no-match value (e.g., pulled down to a logic low value), thereby indicating that a match has not occurred. A ternary CAM cell storing a “don't care” value will provide a match condition for any data value applied to that CAM cell. This “don't care” capability allows CAM arrays to indicate when a data value matches a selected group of ternary CAM cells in a row of the CAM array. For example, assume each row of a ternary CAM array has eight ternary CAM cells. Additionally assume that the each of the first four ternary CAM cells of each row each store one of a logic high and a logic low value (for comparison to the first four bits of an input 8-bit data value) and the each of the last four ternary CAM cells of each row store “don't care” values. Under these conditions, when an 8-bit data value is applied to the ternary CAM array, a match occurs for each row of the CAM array in which the data values stored in the first four ternary CAM cells match the first four bits of the applied 8-bit data value. A read operation for all eight ternary CAM cells will provide meaningful data (e.g., a logic high or logic low value) for each of the first four ternary CAM cells, but only a “don't care” value for each of the last four ternary CAM cells.
A four-state CAM cell operates similarly to the ternary CAM cell described above. However, the “don't care” data capability of the four-state CAM cell additionally allows meaningful “don't care” data (e.g., a logic high “don't care” or a logic low “don't care”) to be stored in the CAM cell. For example, assume each row of a four-state CAM array has eight four-state CAM cells. Additionally assume that the each of the first four four-state CAM cells of each row each store one of a logic high and a logic low value (for comparison to the first four bits of an input 8-bit data value) and the each of the last four four-state CAM cells of each row store one of a logic high “don't care” and a logic low “don't care” value. Similar to the ternary CAM cell example above, under these conditions, when an 8-bit data value is applied to the four-state CAM array, a match occurs for each row of the CAM array in which the data values stored in the first four four-state CAM cells match the first four bits of the applied 8-bit data value. However, a read operation for all eight four-state CAM cells will provide meaningful data (e.g., a logic high “don't care” or a logic low “don't care) for each of the last four four-state CAM cells as well as meaningful data (e.g., a logic high or logic low value) for each of the first four four-state CAM cells.
FIG. 1
is a schematic diagram of a conventional ternary CAM cell
100
. CAM cell
100
includes two 6-transistor (6-T) static random access memory (SRAM) cells
101
A and
101
B (i.e., storage elements
101
A and
101
B) and a 4-T exclusive-NOR circuit
101
C (i.e., comparator
101
C). Thus, CAM cell
100
is a 16-T CAM cell. SRAM cell
101
A includes n-channel transistors
110
,
111
,
114
, and
115
and p-channel transistors
122
and
123
. Transistors
114
,
115
,
122
, and
123
are cross-coupled to form a storage latch having storage node N
1
and inverted storage node N
1
#. Access transistors
110
and
111
couple storage node N
1
# and N
1
, respectively, to inverted bit line B
1
# and bit line B
1
, respectively. Similarly, SRAM cell
101
B includes n-channel transistors
116
and
117
and p-channel transistors
124
and
125
, which are cross-coupled to form a storage latch having node N
2
and inverted storage node N
2
#, and access transistors
112
and
113
, which couple storage nodes N
2
# and N
2
, respectively, to inverted bit line B
2
# and bit line B
2
, respectively. Exclusive NOR circuit
101
C includes n-channel transistors
118
-
121
. Transistors
1

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