Demodulators – Frequency shift keying or minimum shift keying demodulator
Reexamination Certificate
2002-03-01
2003-09-09
Ton, My-Trang Nu (Department: 2816)
Demodulators
Frequency shift keying or minimum shift keying demodulator
C329S304000
Reexamination Certificate
active
06617917
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2001-20497 filed on Apr. 17, 2001.
BACKGROUND
1. Technical Field
The present invention relates to a caller identification (ID) demodulator for demodulating caller ID information, and more particularly, to a caller ID demodulating apparatus and method for demodulating caller ID information using multiple thresholds.
2. Description of Related Art
Telephone companies currently provide various services such as a caller ID service to their subscribers by mounting micro-controllers and LCDs on wired or wireless telephones. For a caller ID service, a central office transmits caller ID information to a called subscriber's telephone terminal by modulating the caller ID in a continuous phase frequency shift keying (CPFSK) format (which is one type of FSK modulation). The CPFSK modulation indicates that the phase of an FSK modulated analog signal is continuous at both a stop point of previous data and a start point of next data, on a time axis, during data transfer.
A zero crossing detection technique is typically used in demodulating FSK modulated signals. The technique extracts zero crossing intervals from a FSK modulated signal and demodulates the FSK modulated signal to a zero (0) or one (1).
Further, white Gaussian noise is added to a binary FSK modulated signal during signal transmission so that zero crossing intervals of the FSK modulated signal are distributed at “0” and “1” regions as a Gaussian curve.
FIG. 1
shows a distribution of the zero crossing intervals of a binary FSK modulated signal. Referring to
FIG. 1
, the zero crossing intervals of the binary FSK modulated signal are distributed in Gaussian curves, in which centers “a” and “b” of the Gaussian curves respectively correspond to zero (0) and one (1) and the curves are symmetric with each other.
A conventional caller ID demodulation method comprises setting an appropriate threshold, and determining whether the zero crossing interval of received data is greater or less than the threshold to determine whether the data is “1” or “0”. However, since the phase of a CPFSK-modulated signal varies randomly in caller ID information service, the zero crossing interval of the modulated signal is distributed over a wide range unlike in FIG.
1
. Thus, a conventional method that uses only one threshold for determining “0” or “1”, such as shown in
FIG. 1
, has disadvantage of causing errors during data demodulation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a caller identification (ID) demodulator using multiple thresholds suitable for continuous phase frequency shift keying (CPFSK) demodulation.
It is another object of the present invention to provide a caller ID demodulation method using multiple thresholds for data demodulation.
It is another object of the present invention to provide a clock signal generator for generating clock signal to demodulate data in a caller ID demodulator.
It is further object of the present invention to provide a clock signal generation method for generating clock signal to demodulate data in caller ID demodulator.
According to one aspect of the invention, it is provided a demodulator for demodulating caller identification (ID) information modulated in a continuous phase frequency shift keying (CPFSK) format. The demodulator comprises a zero crossing detector for generating pulses at points where the modulated caller ID information crosses zero and outputs each pulse as a zero crossing signal, a data extractor for computing a zero crossing interval between each output pulse of the zero crossing signal, and comparing the zero crossing interval with a plurality of thresholds to generate extracted data; and a clock generator for generating a data recovery clock signal for recovering the extracted data in response to the extracted data, wherein the data recovery clock signal is enabled at the middle point of the unit data length of the extracted data.
In one embodiment of the present invention, the extracted data comprises first extracted data having a logic value of high and second extracted data having a logic value of low.
According to another aspect of the invention, it is provided a method for demodulating caller identification (ID) information modulated in a continuous phase frequency shift keying (CPFSK) format. The method comprises the steps of receiving the CPFSK-modulated caller ID information and generating a zero crossing signal, wherein the zero crossing signal comprises pulses produced at points where the modulated caller ID information crosses zero, calculating a zero crossing interval between pulses of the zero crossing signal, comparing the zero crossing interval with a plurality of thresholds to generate extract data, and generating a data recovery clock signal for recovering the extracted data, wherein the data recovery clock signal is enabled at the middle point of the unit data length of the extracted data.
According to another aspect, it is provided an apparatus for generating a data recovery clock signal that is used for recovering data extracted from a demodulator. The apparatus comprises an edge detector for detecting a rising or falling edge of the extracted data and outputting the detected edge as an edge detection signal, a clock counter for counting the number of cycles of a system clock signal, wherein the clock counter is reset in response to the edge detection signal or when the number of the cycles is n+1 (where n>1), a clock generator for generating a data recovery clock signal for recovering the extracted data, wherein the data recovery clock signal is enabled when the number of the cycles is n/2 and is disabled in response to a reset signal, and a reset signal generator for generating the reset signal.
In one embodiment of the present invention, the time for counting the number of cycles of the system clock signal up to n corresponds to the time corresponding to a unit data length of the extracted data.
According to further aspect of the present invention, it is provided a method for generating a data recovery clock signal that is used for recovering data extracted from a demodulator. The method comprises the steps of initializing the number of cycles of a system clock signal, counting the number of cycles of the system clock signal until n/2 (where n>1) and generating a data recovery clock signal when the number of the cycles is n/2, determining whether a rising or falling edge of the extracted data is detected while the number of the cycles is greater than n/2 and less than n, and disabling the data recovery clock signal when the edge of the extracted data is detected or the number of the cycles is n.
REFERENCES:
patent: 4115738 (1978-09-01), Mitarai et al.
patent: 5469112 (1995-11-01), Lee
patent: 5754606 (1998-05-01), Matsuyama et al.
patent: 6272184 (2001-08-01), Ta et al.
Kim Il-joong
Yang Chung-gil
F. Chau & Associates LLP
Nu Ton My-Trang
Samsung Electronics Co,. Ltd.
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