Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2000-01-14
2004-03-30
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S240000, C712S237000, C712S043000, C711S206000, C711S208000
Reexamination Certificate
active
06715063
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of processors and, more particularly, to address and operand sizes in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes.
Unfortunately, the x86 architecture is limited to a maximum 32 bit operand size and 32 bit address size. The operand size refers to the number of bits operated upon by the processor (e.g. the number of bits in a source or destination operand). The address size refers to the number of bits in an address generated by the processor. Thus, processors employing the x86 architecture may not serve the needs of applications which may benefit from 64 bit address or operand sizes.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a processor as described herein. The processor supports a first processing mode in which the address size is greater than 32 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the first processing mode. The first processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state).
While the compatibility modes may allow 32 bit or 16 bit code to execute while the first processing mode is enabled via the enable indication, it may be desirable to call code operating in the first processing mode from the 32 bit or 16 bit code. For example, the operating system may operate in the first processing mode while application programs may operate in 32 or 16 bit mode. A call gate descriptor is defined which occupies two entries in a segment descriptor table. By occupying two entries, each of which may otherwise store a segment descriptor, the call gate descriptor may include enough space to store an address in excess of 32 bits. Thus, a calling code segment may reference a call gate descriptor, which may reference the target code segment and may provide an address within the address space of the target code segment, even if the address exceeds the address size in the calling code segment. Furthermore, by having the call gate descriptor occupy two entries, the segment descriptor table may continue to store segment descriptors for compatibility mode segments. Thus, call gate descriptors and compatibility mode segment descriptors may coexist in the segment descriptor table. Additionally, the area which would be the type field in the second entry occupied by the call gate descriptor may be coded to an invalid type, so that an inadvertent use of the second entry for a code segment may result in the processor signalling an exception.
Broadly speaking, a processor is contemplated. The processor comprises an execution core configured to execute a branch instruction specifying a segment selector. The processor is configured to read at least a first entry from a segment descriptor table responsive to the segment selector, and, if the first entry indicates a call gate descriptor, a second entry in the segment descriptor table stores a remaining portion of the call gate descriptor. Additionally, a computer system is contemplated comprising the processor and an input/output (I/O) device configured to communicate between the computer system and another computer system to which the I/O device is couplable.
Moreover, A method is contemplated. A call gate descriptor is read from a segment descriptor table. The call gate descriptor comprises a first entry and a second entry in the segment descriptor table, wherein each of the first entry and the second entry is capable of storing a segment descriptor. An offset is extracted from the call gate descriptor. The offset locates a first instruction to be executed in a target code segment.
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Advanced Micro Devices , Inc.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Pan Daniel H.
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