Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
1998-05-26
2001-05-29
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S758010
Reexamination Certificate
active
06239590
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a calibration target for calibrating semiconductor wafer test systems including wafer handlers and probe card analyzers. This invention also relates to a method for fabricating the calibration target and to a test method employing the probe card.
BACKGROUND OF THE INVENTION
Semiconductor wafers are tested prior to singulation into individual dice, to assess the electrical characteristics of the integrated circuits contained on the dice. A typical wafer-level test system includes a wafer handler for handling and positioning the wafer, a tester for generating test signals, a probe card for making temporary electrical connections with the wafer, and a prober interface board for routing signals from tester pin electronics of the tester, to the probe card.
The probe card includes probe contacts adapted to make temporary electrical connections with wafer contacts on a wafer under test (WUT). Typically, the wafer contacts comprise bond pads, test pads, or fuse pads formed on the dice contained on the wafer. The most common type of probe card includes needle probes formed on a rigid substrate. Another type of probe card, known as a membrane probe card, includes metal microbumps on a flexible substrate. Yet another type of probe card includes a silicon substrate and raised probe contacts covered with conductive layers.
Because probe cards are expensive, it is advantageous to maintain probe cards by periodically assessing dimensional characteristics, such as the X,Y alignment and the planarity of the probe contacts on a probe card. Various electrical characteristics such as contact resistance of the probe contacts, and current leakage in the probe card can also be assessed. In order to evaluate these dimensional and electrical characteristics, probe card inspecting apparatus have been developed. These probe card inspecting apparatus are sometimes referred to as “probe card analyzers”. U.S. Pat. Nos. 4,918,374; 5,060,371 and 5,508,629 to Stewart et al. describe probe card analyzers. In addition, probe card analyzers are commercially available from Applied Precision, Inc., Mercer Island, Wash.
For calibrating a probe card analyzer, a calibration target can be used in place of the probe cards. The calibration target includes alignment features similar in size and shape to the probe contacts. The alignment features are adapted for viewing by viewing devices associated with a check plate, or alignment system of the probe card analyzer. This permits the check plate, and a probe card chuck associated with the check plate, to be aligned in X and Y directions. Other alignment features on the calibration target can be electrically conductive to permit alignment in the Z direction upon completion of an electrical circuit. Once the probe card analyzer has been calibrated, the calibration target can be removed, and replaced with probe cards for evaluation.
In addition to calibrating probe card analyzers, calibration targets can also be used to calibrate the wafer handler of the wafer test system. For example, a wafer chuck contained on the wafer handler of the test system is constructed to move in the X and Y directions, to align the probe contacts to the wafer contacts, and in the Z direction to move the probe contacts into physical and electrical contact with the wafer contacts. A typical wafer chuck comprises a platform mounted on rails or other guiding mechanism. The platform can be moved in X, Y and Z directions by suitable linear actuators, such as a ball screw and motor, to precisely position the wafer under test with respect to the probe card. Some wafer chucks also include provision for alignment in a rotational direction (e.g., &thgr;). The wafer handler can also include an optical, or mechanical, alignment system for controlling the wafer chuck to align the wafer and probe card. For calibrating the wafer chuck and the alignment system, a calibration target can be mounted on the wafer chuck proximate to a probe card to simulate a wafer under test.
Conventional calibration targets are typically manufactured of glass, or metal, and have thick film alignment features. Stenciling is a conventional method for forming the alignment features on the calibration target. Although this type of calibration target has been used successfully in the industry, the probe contacts are becoming increasingly smaller and more densely spaced to accommodate smaller and denser wafer contacts. For example, bond pads can be about 50 microns wide on a 50 micron pitch, which is the current state of the art for wire bonding capability. As the industry progresses, smaller and denser bond pads are predicted. Accordingly, the probe contacts must correspond in size to the wafer contacts. In general, stenciled calibration targets are not able to provide the accuracy necessary to allow precision calibration of probe card analyzers and wafer test systems.
Another problem with conventional calibration targets is that printed alignment features can be damaged with continued usage. For example, an alignment feature which has been scratched, or obliterated, can be difficult to view, thus making accurate alignment difficult.
In view of the foregoing, it would be advantageous to provide a calibration target having high contrast alignment features formed with a high degree of accuracy. In addition, alignment features which are three dimensional would improve the viewability of the features, and allow calibration in the Z-direction, as well as in the X and Y directions. It would also be advantageous to provide a calibration target having alignment features that are damage resistant to permit extended use in a production environment.
SUMMARY OF THE INVENTION
In accordance with the present invention, a calibration target for calibrating wafer test systems including wafer handlers and probe card analyzers is provided. Also provided are a method for fabricating the calibration target, and calibration methods using the calibration target.
The calibration target, simply stated, comprises a substrate, and patterns of alignment features formed on the substrate. The alignment features are three dimensional raised members, or alternately three dimensional recessed members, formed integrally with the substrate. Each alignment feature is covered with a metal contrast layer, and includes one or more metal fiducials formed on a surface thereof. Preferably, either the contrast layers, or the alignment features, comprises a highly reflective metal, such as aluminum or chromium. The fiducials are adapted for viewing by a viewing device of the probe card analyzer, or of the test system, against the background provided by the contrast layers.
A first type of alignment feature comprises a pillar, or alternately an elongated ridge, having one or more fiducials thereon. A second type of alignment feature comprises a pillar having a planar surface with a dense pattern of fiducials. A third type of alignment feature includes a conductive layer rather than fiducials, and is adapted to perform z-direction and planarity calibration. The conductive layer includes a bonding pad, or alternately a conductive via, for forming an electrical path between the alignment feature and a continuity circuit. A fourth type of alignment feature comprises a recess in the substrate having a fiducial formed thereon.
A method for fabricating the calibration target includes the steps of providing the substrate (e.g., silicon), and initially blanket depositing a reflective layer (e.g., chromium, aluminum) on the substrate. A first mask (e.g., resist mask) is then formed, and used to etch the reflective layer to form contrast layers in areas that will subsequently be the surfaces of the alignment features. A second mask is then formed in order to etch the substrate to form the alignment features. Preferably, the second mask comprises a hard mask (e.g., Si
3
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4
) having solid portions that cover the previously formed contrast layers. Using the second mask, and a suitable wet etchant (e.g., KOH), the substrate is etched to form the a
Akram Salman
Farnworth Warren M.
Hembree David R.
Jacobson John O.
Krivy Andrew J.
Gratton Stephen A.
Micro)n Technology, Inc.
Nguyen Vinh P.
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