Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-31
2008-10-28
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
07444615
ABSTRACT:
A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.
REFERENCES:
patent: 7269804 (2007-09-01), Tabery et al.
Horng Chi-Song
Percin Gokhan
Prasad Roy
Ramanujam Ram S.
Sezginer Abdurrahman
Do Thuan
Invarium, Inc.
Sheppard Mullin Richter & Hampton LLP
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