Calibration of memory driver with offset in a memory...

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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C365S201000

Reexamination Certificate

active

07848175

ABSTRACT:
A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. The memory device, which is typically the device initializing a bit level voltage on a data net, is adjusted through altering what appears to be the reference voltage value to the memory device. A current driven to the memory device is varied in small increments while impedance training is rerun until a desired value is achieved to set the 0 level voltage on the data net.

REFERENCES:
patent: 6330194 (2001-12-01), Thomann et al.
patent: 6762614 (2004-07-01), Rearick et al.
patent: 7514954 (2009-04-01), Kim et al.
patent: 7515487 (2009-04-01), Seo et al.

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