Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2011-04-19
2011-04-19
Cho, James (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S027000
Reexamination Certificate
active
07928757
ABSTRACT:
Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.
REFERENCES:
patent: 4513427 (1985-04-01), Borriello
patent: 4707620 (1987-11-01), Sullivan et al.
patent: 5254883 (1993-10-01), Horowitz
patent: 5298800 (1994-03-01), Dunlop
patent: 5396028 (1995-03-01), Tomassetti
patent: 5455844 (1995-10-01), Ishikawa
patent: 5467455 (1995-11-01), Gay et al.
patent: 5606275 (1997-02-01), Farhang et al.
patent: 5663661 (1997-09-01), Dillon
patent: 5666078 (1997-09-01), Lamphier et al.
patent: 5680060 (1997-10-01), Banniza
patent: 5726582 (1998-03-01), Hedberg
patent: 5745011 (1998-04-01), Scott
patent: 5781028 (1998-07-01), Decuir
patent: 5864506 (1999-01-01), Arcoleo et al.
patent: 5864587 (1999-01-01), Hunt
patent: 5926031 (1999-07-01), Wallace
patent: 5958026 (1999-09-01), Geotting et al.
patent: 5969658 (1999-10-01), Naylor
patent: 5995894 (1999-11-01), Wendte
patent: 6028484 (2000-02-01), Cole
patent: 6052035 (2000-04-01), Nolan
patent: 6060907 (2000-05-01), Vishwanthaiah et al.
patent: 6064224 (2000-05-01), Esch, Jr.
patent: 6127862 (2000-10-01), Kawasumi
patent: 6157206 (2000-12-01), Taylor et al.
patent: 6166563 (2000-12-01), Volk et al.
patent: 6266001 (2001-07-01), Fang
patent: 6288564 (2001-09-01), Hedberg
patent: 6291881 (2001-09-01), Yang
patent: 6297759 (2001-10-01), Lewyn
patent: 6297795 (2001-10-01), Kato et al.
patent: 6308232 (2001-10-01), Gasbarro
patent: 6330193 (2001-12-01), Yu
patent: 6344765 (2002-02-01), Taguchi
patent: 6356105 (2002-03-01), Volk
patent: 6356106 (2002-03-01), Greef et al.
patent: 6356114 (2002-03-01), Selander
patent: 6411122 (2002-06-01), Mughal
patent: 6418500 (2002-07-01), Gai
patent: 6424170 (2002-07-01), Raman
patent: 6429679 (2002-08-01), Kim et al.
patent: 6442644 (2002-08-01), Gustavson et al.
patent: 6445331 (2002-09-01), Stegers
patent: 6448813 (2002-09-01), Donnelly et al.
patent: 6462588 (2002-10-01), Lau
patent: 6462591 (2002-10-01), Garrett, Jr.
patent: 6467013 (2002-10-01), Nizar
patent: 6495997 (2002-12-01), Hall et al.
patent: 6509756 (2003-01-01), Yu
patent: 6511901 (2003-01-01), Lam
patent: 6516365 (2003-02-01), Horowitz
patent: 6525558 (2003-02-01), Kim
patent: 6530062 (2003-03-01), Donnelly et al.
patent: 6531784 (2003-03-01), Shim, II
patent: 6541996 (2003-04-01), Rosefield et al.
patent: 6545522 (2003-04-01), Mughal
patent: 6552565 (2003-04-01), Chang
patent: 6573746 (2003-06-01), Kim
patent: 6573747 (2003-06-01), Radhakrishnan
patent: 6597298 (2003-07-01), Kim
patent: 6606004 (2003-08-01), Staszewski
patent: 6608507 (2003-08-01), Garrett, Jr.
patent: 6643787 (2003-11-01), Zerbe
patent: 6661250 (2003-12-01), Kim
patent: 6711073 (2004-03-01), Martin
patent: 6717455 (2004-04-01), Mughal et al.
patent: 6734702 (2004-05-01), Ikeoku et al.
patent: 6762620 (2004-07-01), Jang et al.
patent: 6768352 (2004-07-01), Maher
patent: 6771073 (2004-08-01), Henningson
patent: 6781405 (2004-08-01), Best et al.
patent: 6781406 (2004-08-01), Emberling et al.
patent: 6781416 (2004-08-01), Nguyen et al.
patent: 6806728 (2004-10-01), Nguyen
patent: 6812735 (2004-11-01), Pham
patent: 6833729 (2004-12-01), Kim et al.
patent: 6853938 (2005-02-01), Jeddeloh
patent: 6856169 (2005-02-01), Frans
patent: 6894691 (2005-05-01), Juenger
patent: 6924660 (2005-08-01), Nguyen
patent: 6940303 (2005-09-01), Vargas
patent: 6965529 (2005-11-01), Zumkeher et al.
patent: 7102200 (2006-09-01), Fan et al.
patent: 7148721 (2006-12-01), Park
patent: 7151390 (2006-12-01), Nguyen
patent: 7230448 (2007-06-01), Choe
patent: 2001/0047450 (2001-11-01), Gillingham et al.
patent: 2002/0141896 (2002-10-01), Komazaki
patent: 2002/0175716 (2002-11-01), Cyrusian
patent: 2003/0087671 (2003-05-01), Ruha et al.
patent: 2004/0124850 (2004-07-01), Koneru
patent: 2004/0201402 (2004-10-01), Rajan
patent: 2005/0041683 (2005-02-01), Kizer
patent: 2005/0052200 (2005-03-01), Nguyen
patent: 2005/0057278 (2005-03-01), Nguyen
patent: 2006/0007761 (2006-01-01), Ware
patent: 2006/0077731 (2006-04-01), Ware
patent: 0482336 (1992-04-01), None
patent: 02140676 (1990-05-01), None
patent: WO 97/02658 (1997-01-01), None
patent: WO 98/04041 (1998-01-01), None
patent: WO 00/41300 (2000-07-01), None
patent: WO 00/70474 (2000-11-01), None
patent: WO 02/37781 (2002-05-01), None
patent: WO 0237781 (2002-05-01), None
patent: WO 2004/061690 (2004-07-01), None
Nakase, Yasunobu, et al., “Source-Synchronization and Timing Vernier Techniques for 1.2 GB/s SLDRAM Interface,” IEEE Journal of Solid-State Circuits, vol. 34, No. 4, Apr. 1999, pp. 494-501.
“Hastings Rambus Asic Cell Specification Generic Implementation, Revision 0.1 Preliminary.” Copyright 1999 Rambus Inc. Modified Jun. 20, 2000 149 pages.
Khouri, Gaby “Evaluation of Alcatel Patent Portfolio by Semiconductor Insights.” Nov. 2004. Copyright Semiconductor Insights Inc. 38 pages.
Knight, Thomas F. Jr., “A Self-Terminating Low-Voltage Swing CMOS Output Driver.” IEEE Journal of Solid-State Circuits, vol. 23, No. 2, Apr. 1988. pp. 457-464.
Paris et al., “WP 24.3: A 800 MB/s 72 Mb SLDRAM with Digitally-Calibrated DLL,” ISSCC, 0-7803-5129-0/99, 10 pages. Slide Supplement, IEEE, 1999.
SLDRAM Inc., “400 Mb/s/pin SLDRAM” Draft/Advance, “4M x 18 SLDRAM, Pipelined, Eight Bank, 2.5V Operation.” Rev. Jul. 9, 1998, pp. 1-69, Copyright 1998.
“Intel 430 TX PCISET:824395TX System Controller (MTXC)”. Preliminary. Order No. 290559-001. Copyright Feb. 1997, Intel Corporation. 84 pages.
Gillingham, Peter, “SLDRAM Architectural and Functional Overview,” Aug. 1997, pp. 1-14.
Babcock, J.A., “Precision Electrical Trimming of Very Low TCR Poly-SiGe Resistors.” IEEE Electron Device Letters, vol. 21, No. 6, Jun. 2000, pp. 283-285.
Gabara, Thaddeus J., “On-Chip Terminating Resistors for High Speed ECL-CMOS Interfaces.” Feb. 1992. IEEE. pp. 292-295.
Ware, Frederick A., “Direct RAC Data Sheet.” Advance Information. Document DL0064, Version 1.11. Copyright Jul. 2000, Rambus Inc. 66 pages.
Micron, “Graphics DDR3 DRAM.” Advance. “256 Mb×32 GDDR3 DRAM.” © 2003 Micron Technology, Inc. pp. 1-67.
Shah, Sunay et al., “A Temperature Independent Trimmable Current Source.” Department of Engineering Science, University of Oxford. ISCAS 2002. 4 pages.
Ko, Hyoung-Soo, “Development of 3-Dimensional Memory Die Stack Packages Using Polymer Insulated Sidewall Technique.” 1999 Electronic Components and Technology Conference. pp. 663-667.
Johnson, Chris. “The Future of Memory: Graphics DDR3 SDRAM Functionality.” Micron Designline, vol. 11, Issue 4, 4Q02. 8 pages.
Diermeier, Andrea. “Interfacing between LVDS and ECL”, Microprocessors and Microsystems, IPC Business Press LTD, London GB, vol. 21 No. 5, Feb. 1998, pp. 337-342.
Gabara, Thaddeus J. et al., “Digitally Adjustable Resistors in CMOS for High-Performance Applications,” IEEE Journal of Solid State Circuits, IEEE Inc. New York, US, vol. 27, No. 8, Aug. 1, 1992, pp. 1176-1185, XP000309397 ISSN: 0018-9200.
Patent Cooperation Treaty, International Search Report and Opinion of International Search Authority in re Application No. PCT/US2004/014150, Jun. 28, 2005, 21 pages.
Al-Sarawi, Said F., “A Review of 3-D Packaging Technology.” IEEE Transaction on Components, Pack
Gadde Vijay
Lau Benedict
Nguyen Huy M.
Behiel Arthur J.
Cho James
Rambus Inc.
Silicon Edge Law Group LLP
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