Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-12-27
2005-12-27
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C327S108000
Reexamination Certificate
active
06980020
ABSTRACT:
Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a transmitter die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains the termination resistances for the signal transmission lines. The ODT control system derives a number of calibration currents from precision voltage and resistance references and distributes the reference currents to a number of transmitters. Each transmitter then derives an ODT calibration signal using the respective reference current and another precision resistor, and then employs the calibration signal to calibrate local termination elements. Distributing calibrated currents provides excellent noise immunity, while limiting the requisite number of external voltage references reduces cost.
REFERENCES:
patent: 4513427 (1985-04-01), Borriello et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5298800 (1994-03-01), Dunlop et al.
patent: 5396028 (1995-03-01), Tomassetti
patent: 5680060 (1997-10-01), Banniza et al.
patent: 5926031 (1999-07-01), Wallace et al.
patent: 5969658 (1999-10-01), Naylor
patent: 6028484 (2000-02-01), Cole et al.
patent: 6064224 (2000-05-01), Esch, Jr. et al.
patent: 6266001 (2001-07-01), Fang et al.
patent: 6297759 (2001-10-01), Lewyn
patent: 6344765 (2002-02-01), Taguchi
patent: 6411122 (2002-06-01), Mughal et al.
patent: 6418500 (2002-07-01), Gai et al.
patent: 6424170 (2002-07-01), Raman et al.
patent: 6462591 (2002-10-01), Garrett, Jr. et al.
patent: 6467013 (2002-10-01), Nizar
patent: 6525558 (2003-02-01), Kim et al.
patent: 6530062 (2003-03-01), Liaw et al.
patent: 6545522 (2003-04-01), Mughal et al.
patent: 6573746 (2003-06-01), Kim et al.
patent: 6573747 (2003-06-01), Radhakrishnan
patent: 6597298 (2003-07-01), Kim et al.
patent: 6606004 (2003-08-01), Staszewski et al.
patent: 6661250 (2003-12-01), Kim et al.
patent: 6734702 (2004-05-01), Ikeoku et al.
patent: 6762620 (2004-07-01), Jang et al.
patent: 6768352 (2004-07-01), Maher et al.
Gabara, Thaddeus J. et al. “A 200 MHz 100K ECL Output Buffer for CMOS ASICs.” 1990 IEEE. p. 4, no mo.
Gabara, Thaddeus J., “On-Chip Terminating Resistors for High Speed ECL-CMOS Interfaces.” Feb. 1992. IEEE. pp. 292-295.
Knight, Thomas F. Jr., “A Self-Terminating Low-Voltage Swing CMOS Output Driver.” IEEE Journal of Solid-State Circuits, vol. 23, No. 2, Apr. 1988. pp. 457-464.
Gabara, Thaddeus J., “Digitally Adjustable Resistors in CMOS for High-Performance Applications.” IEEE Journal of Solid-State Circuits, vol. 27, No. 8, Aug. 1992. pp. 1176-1185.
Babcock, J.A., “Precision Electrical Trimming of Very Low TCR Poly-SiGe Resistors.” IEEE Electron Device Letters, vol. 21, No. 6, Jun. 2000. pp. 283-285.
Shah, Sunay et al., “A Temperature Independent Trimmable Current Source.” Department of Engineering Science, University of Oxford. ISCAS 2002. 4 pages, no. mo.
Kim, Su-Chul, “Programmable Digital On-Chip Terminator.” ITC-CSCC, 2002. 4 pages, no mo.
Best Scott C.
Leung David
Wong Anthony Koon
Behiel Arthur J.
Chang Daniel
Rambus Inc.
Silicon Edge Law Group LLP
LandOfFree
Calibration methods and circuits for optimized on-die... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Calibration methods and circuits for optimized on-die..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Calibration methods and circuits for optimized on-die... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3517605