Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-06-26
2010-02-02
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S087000
Reexamination Certificate
active
07656186
ABSTRACT:
A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impedance adjustments of the replica buffers; and a 32 tCK cycle counter that forcibly activates the latch circuits in response to a lapse of a predetermined period since issuance of the calibration command. Thereby, even when the adjustment is not completed during one calibration period, a subsequent calibration operation can be executed from a previous point.
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patent: 2008/0001624 (2008-01-01), Lee
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Fujisawa Hiroki
Osanai Fumiyuki
Elpida Memory Inc.
Le Don P
McGinn IP Law Group PLLC
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