Calibration circuit, semiconductor device including the...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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Details

C327S170000, C365S189110

Reexamination Certificate

active

07902858

ABSTRACT:
A calibration circuit includes: a replica buffer that drives a calibration terminal; a pre-emphasis circuit connected in parallel to the replica buffer; and an up-down counter that changes impedances of the replica buffer and the pre-emphasis circuit. A replica control circuit causes the replica buffer to conduct based on an impedance code, and a pre-emphasis control circuit causes the pre-emphasis circuit to conduct in an initial stage of a conducting period of the replica buffer. Thereby, even when an external resistor is shared among a plurality of semiconductor devices, for example, a voltage appearing in the calibration terminal can be stabilized at a higher speed.

REFERENCES:
patent: 6839286 (2005-01-01), Cho et al.
patent: 7521957 (2009-04-01), Koo
patent: 2003/0231523 (2003-12-01), Cho et al.
patent: 2006/0006903 (2006-01-01), Choi et al.
patent: 2009/0009213 (2009-01-01), Osanai et al.
patent: 2002-152032 (2002-05-01), None
patent: 2004-32070 (2004-01-01), None
patent: 2005-159702 (2005-06-01), None
patent: 2006-203405 (2006-08-01), None
patent: 2007-110615 (2007-04-01), None

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