Calibration circuit

Details Calibration circuit Calibration circuit

2011-01-18

2011-01-18

Cho, James (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S021000

Reexamination Certificate

active

07872493

ABSTRACT:
In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK1to both a hit determination circuit and a second clock gate circuit. The second clock gate circuit110passes through the first update clocks CLK1until reception of a hit signal from the hit determination circuit and delivers second update clocks CLK2to an up/down counter106. The up/down counter106is operated by the second update clocks CLK2. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.

REFERENCES:
patent: 6919738 (2005-07-01), Kushida
patent: 7038486 (2006-05-01), Aoyama et al.
patent: 7084662 (2006-08-01), Om et al.
patent: 7221193 (2007-05-01), Wang et al.
patent: 2008/0046212 (2008-02-01), Yoko et al.
patent: 2008-048361 (2008-02-01), None

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