Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-11
2007-12-11
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C714S724000, C714S738000, C714S741000
Reexamination Certificate
active
10758446
ABSTRACT:
A calculation system of fault coverage includes a data acquiring module acquiring layout information and gate net data, a layout analysis and fault link module extracting a layout element information and generating a undetected fault list, a fault detecting module generating a detected and undetected fault list, and a weight calculating module adding layout element information as weight, based on a link file between faults and layout element information to be generated based on the layout information, the gate net data, and the detected and undetected fault list.
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Official Action Letter issued Mar. 27, 2007 in counterpart Japanese application with English translation.
Sengupta, S. et al., “Defect-Based Test: A Key Enabler For Successful Migration To Structural Test,” Intel Technology Journal, pp. 1-14, Q1 '99.
DLA Piper (US) LLP
Kabushiki Kaisha Toshiba
Siek Vuthe
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