Calculating interconnect swizzling patterns for capacitive...

Details Calculating interconnect swizzling patterns for capacitive... Calculating interconnect swizzling patterns for capacitive...

2001-12-28

2003-08-26

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06611944

ABSTRACT:

FIELD OF THE DISCLOSURE
This disclosure relates generally to the field of interconnect systems and circuits for transmission of digital data. In particular, the disclosure relates to line swizzling which may result in the reduction of inductive and capacitive noise on multiple-line interconnects.
BACKGROUND OF THE DISCLOSURE
As signals in electronic devices switch at higher and higher frequencies, maintaining the integrity of these signals becomes an increasingly difficult problem. High frequency signaling and smaller feature sizes made possible by advanced processing techniques increase the importance of signal integrity and signal timing. Additionally, wider bus interconnects, faster switching rates and higher scales of integration increase the potential for signal noise and related failures.
Capacitive coupling and inductive coupling of concurrently switched signal lines may combine to produce worst-case signal noise that results in one or more noise failures or noise-induced timing failures.
Techniques such as shielding and line reordering have been used, especially to reduce the short-range effects of capacitive coupling. Inductive shielding, consisting of fixed-potential or ground lines between sets of signal lines, has also been used, especially in higher metal layers but shielding lines (or return lines) consume signal tracks and can be costly, especially in interconnect-limited designs.
Insertion of repeaters has been used to improve signal integrity and limit noise effects, but repeaters also require additional area and have a further drawback of consuming additional power.
Isolating signal lines between two metal planes has been used in some commercial processor designs to limit on-chip inductive coupling, but may require that relatively large areas of existing metal layers or even additional metal layers be used as isolating metal planes.
Reordering a set of signal lines with respect to a shared return line has been shown to reduce inductive coupling between the reordered set and another set of signal lines, but this technique alone has not previously been shown to be effective in reducing the inductance within the reordered set. Further, this technique requires at least as many reordering stages as signal lines in the reordered set.


REFERENCES:
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Guoan Zhong, Cheng-Kok Koh, Kauskik Roy, “A Twisted-Bundle Layout Structure for Minimizing Inductive Coupling Noise,” International Conference on Computer-Aided Design, Nov. 5-9, 2000, School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285.

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