Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-06-19
2007-06-19
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10955532
ABSTRACT:
One embodiment of the present invention provides a system that calculates etch proximity-correction during an OPC (Optical Proximity Correction) process. During operation, the system receives a layout for an integrated circuit. Next, the system selects a target point on an edge in the layout. The system then creates a list of edges within an ambit of the target point. Next, the system removes edges from the list that are not visible from the target point. The system then computes a line integral of a statistical function over the remaining edges in the list, wherein the line integral of the statistical function models the etch proximity effects correlated with positions of the edges visible from the target point. Next, the calculated etch proximity-correction is applied to an area in proximity to the target point.
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Beale Dan
Shiely Jim
Stirniman John
Garbowski Leigh M.
Park Vaughan & Fleming LLP
Synopsys Inc.
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