Calculating a + sign(A) in a single instruction cycle

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36478401, G06F 750

Patent

active

058318860

ABSTRACT:
The expression A+sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementingA, bit-complementing(A+1) when A is less than zero, bit-complementing A when A is equal to zero, bit-complementing(A-1) when A is greater than zero and odd, and bit-complementingall bits except a least significant bit of A when A is greater than zero and even. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A+sign(A) can be calculated by a general purpose computer in a single instruction cycle.

REFERENCES:
patent: 4218751 (1980-08-01), McManigal
patent: 4709226 (1987-11-01), Christopher
patent: 4953115 (1990-08-01), Kanoh
patent: 5267187 (1993-11-01), Hsieh et al.
patent: 5373459 (1994-12-01), Taniguchi
patent: 5574671 (1996-11-01), Young et al.
U.S. Application Serial No. 08/658,454, Filed Jun. 5, 1996, entitled "Zero Detect for Binary Sum" by R. Wong.
U.S. Application Serial No. 08/695,142, Filed Aug. 8, 1996, entitled "Zero Detect for Binary Difference" by R. Wong.

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