Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-26
2003-09-30
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06629300
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a CAD (computer aided design) system for designing an ASIC (application specific integrated circuit) and, more particularly, to a CAD system which is capable of reducing a turn around time (TAT) for the design of an ASIC.
(b) Description of a Related Art
In a fabrication process for a semiconductor device such as ASIC, the technique for designing a system-on-chip LSI including therein a plurality of ICs integrated on a single chip is highlighted. In the field of LSIs for the communication use, the demands for integrating or embedding a higher-speed IC operating with a smaller voltage amplitude or a higher-resolution IC having a higher resolution and a higher-integrated IC operating at a lower speed in a single chip have drastically increased.
Examples of the higher-speed ICs include a logic circuit operating with a low voltage differential signaling (LVDS) and a current mode logic circuit (CML). Examples of the higher-integrated ICs include a CMOS device, which operates with a higher voltage amplitude between source potentials and consumes extremely small current during a waiting mode thereof.
Demands have also increased for designing the embedded LSI including the higher-speed IC and the higher-integrated IC with a smaller TAT. The embedded LSI generally includes in the higher-speed IC a plurality of basic cells each including device elements having a relatively large size, and in the higher-integrated IC a plurality of basic cells each having device elements having a relatively small size and thus occupying a smaller area.
FIG. 1
shows a CAD system used for designing a LSI such as an ASIC (Application Specific Integrated Circuit). The CAD system
11
includes an input section
12
, a library storage
13
, a data processor
14
, a display panel
15
and an output section
16
. In the CAD system, the data processor
14
operates for processing based on the circuit data or user data input through the input section
12
and the library data stored in the library storage
13
, then generates custom mask pattern data in accordance with the requested specification, and delivers the custom mask pattern data through the output section
16
. The custom mask pattern data is generated by using an interactive processing while observing the display panel
15
.
FIG. 2
shows a flowchart of designing a macro block in the CAD system of FIG.
1
. After data for the macro block are read out in step
412
, the size of the macro block, or the number of basic cells to be arranged in row and column directions, is determined based on the read data in step
413
, followed by an automated wiring step for designing interconnections in the macro block. The term “macro block” as used herein means a set of basic cells or functional cells operating for a specific function as a whole. The macro block is categorized into two types: a software macro block and a hardware macro block, the latter being capable of handling the logic signals at a higher speed compared to the former.
Examples of the hardware macro block include a first type having basic electric elements such as transistors, resistors and capacitors which are arranged and interconnected, and a second type having basic logic gates such as NANDs, NORs and flipflops in combination which are arranged and interconnected. The hardware macro block is generally implemented by the second type for achieving a higher-speed or higher-resolution operation. The data for hardware macro blocks are stored in the library storage of the CAD system after examination of the electric characteristics thereof including a timing characteristic. The data stored for the macro block in the library includes fixed information for the dimensions and external pins thereof. On the other hand, the data for software macro blocks in the library include interconnections between logic circuits, and does not include locational information for the elements and the interconnections.
In step
414
, source lines for the semiconductor chip are fixed by an automated wiring technique, and basic cells are then located in step
415
by an automated arrangement technique, followed by automated wiring step
416
for the functional cells, and a subsequent verification step
417
for verifying the electric characteristics such as a timing characteristic. If the test results for the electric characteristics assure a desired operation, the steps for the macro block design are finished. If not, the process returns to step
412
or
413
, for iterative processing for assuring the electric characteristics such as timings.
FIG. 3
shows a flowchart of a chip design in the CAD system of FIG.
1
. In step
422
, the macro block designing process of
FIG. 2
is first conducted, then followed by input of the data for the semiconductor chip in step
423
. In step
424
, one or a plurality of hardware macro blocks are forcibly or manually arranged in a higher-integrated area.
In step
425
, source lines for the chip are arranged by automated wiring, followed by automated arrangement of functional cells in the higher-integrated area in step
426
, and automated wiring of signal interconnections between the functional cells in step
427
. In step
428
, electric characteristics of the resultant chip such as a timing characteristic are examined. If the test results assure the desired operation, the chip design is finished. If not, the process returns to step
422
,
423
or
424
for iterative processing until desired characteristics can be obtained.
FIGS. 4 and 5
are detailed schematic flowcharts of a process shown in FIG.
2
. After the process starts, interconnection information (netlist)
712
for the macro block, pin-arrangement information
713
and an automated arrangement/interconnection library
714
are read from the storage. In step
715
, the size and shape of the hardware macro block are then determined for achieving a higher-speed operation based on the netlist
712
, pin-arrangement information
713
and library
714
, to obtain array information
716
.
FIG. 6
shows an example of the arrangement of resistors and bipolar transistors in one of the functional cells specified by the array information
716
.
Subsequently, in step
717
, source bus line information is added to the array information
716
of the hardware macro block by using an automated arrangement/wiring tool for the macro blocks, to thereby obtain enhanced array information
718
. In step
719
of
FIG. 5
, the enhanced array information
718
is further added with data for type “B” (higher-speed) logic cells, which are manually arranged, to thereby obtain macro block arrangement data
720
.
FIG. 6
shows the arrangement of a higher-speed (or type “B”) logic circuit disposed in a higher-speed area and
FIG. 7
shows a circuit diagram for the logic circuit, which includes bipolar transistors and resistors as well as source lines and signal lines. The source lines include VCC source line, VCSI reference line and GND line. The logic circuit is implemented by a differential circuit or an ECL circuit.
Back to
FIG. 5
, in step
721
, automated wiring is conducted in the ECL circuit based on the macro block information
720
to obtain macro block interconnection data
722
. If desired interconnections are not obtained by the automated wiring step, a manual wiring function included in the automated arrangement/interconnection tool is used for correction of the interconnections obtained by the automated wiring steps. Then, in step
723
, characteristics of the obtained macro blocks are examined based on the macro block interconnection data
722
, followed by judgement of the test results in step
724
If it is judged that desired characteristics are obtained in the macro blocks, the process advances to step
725
or
727
. If it is judged that desired characteristics are not obtained, the process returns to steps
741
and
742
for judgement whether or not correction in the interconnections is sufficient to allow the resultant macro block to pass the
McGinn & Gibb PLLC
NEC Electronics Corporation
Niebling John F.
Whitmore Stacy A
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